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author | Douglas Anderson <dianders@chromium.org> | 2015-07-21 22:41:23 +0200 |
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committer | Stephen Boyd <sboyd@codeaurora.org> | 2015-07-28 20:59:12 +0200 |
commit | 2bbfe00147a7c075f5c43e657ec218afea662819 (patch) | |
tree | 25400d1f396ff92dc53a9153db5af4ebd31cffff /drivers/clk/pxa | |
parent | Merge branch 'cleanup-clk-h-includes' into clk-next (diff) | |
download | linux-2bbfe00147a7c075f5c43e657ec218afea662819.tar.xz linux-2bbfe00147a7c075f5c43e657ec218afea662819.zip |
clk: rockchip: Fix PLL bandwidth
In the TRM we see that BWADJ is "a 12-bit bus that selects the values
1-4096 for the bandwidth divider (NB)":
NB = BWADJ[11:0] + 1
The recommended setting of NB: NB = NF / 2.
So:
NB = NF / 2
BWADJ[11:0] + 1 = NF / 2
BWADJ[11:0] = NF / 2 - 1
Right now, we have:
{ \
.rate = _rate##U, \
.nr = _nr, \
.nf = _nf, \
.no = _no, \
.bwadj = (_nf >> 1), \
}
That means we set bwadj to NF / 2, not NF / 2 - 1
All of this is a bit confusing because we specify "NR" (the 1-based
value), "NF" (the 1-based value), "NO" (the 1-based value), but
"BWADJ" (the 0-based value) instead of "NB" (the 1-based value).
Let's change to working with "NB" and fix the off by one error. This
may affect PLL jitter in a small way (hopefully for the better).
Signed-off-by: Douglas Anderson <dianders@chromium.org>
Reviewed-by: Heiko Stuebner <heiko@sntech.de>
Signed-off-by: Stephen Boyd <sboyd@codeaurora.org>
Diffstat (limited to 'drivers/clk/pxa')
0 files changed, 0 insertions, 0 deletions