diff options
| author | Barnabás Czémán <barnabas.czeman@mainlining.org> | 2024-10-06 22:51:58 +0200 |
|---|---|---|
| committer | Bjorn Andersson <andersson@kernel.org> | 2024-10-15 01:51:29 +0200 |
| commit | e02bfea4d7ef587bb285ad5825da4e1973ac8263 (patch) | |
| tree | 575f706076d8cae89d2b1c45e317bb31d43a4617 /drivers/clk/qcom/clk-alpha-pll.c | |
| parent | clk: qcom: videocc-sm8350: use HW_CTRL_TRIGGER for vcodec GDSCs (diff) | |
| download | linux-e02bfea4d7ef587bb285ad5825da4e1973ac8263.tar.xz linux-e02bfea4d7ef587bb285ad5825da4e1973ac8263.zip | |
clk: qcom: clk-alpha-pll: Fix pll post div mask when width is not set
Many qcom clock drivers do not have .width set. In that case value of
(p)->width - 1 will be negative which breaks clock tree. Fix this
by checking if width is zero, and pass 3 to GENMASK if that's the case.
Fixes: 1c3541145cbf ("clk: qcom: support for 2 bit PLL post divider")
Signed-off-by: Barnabás Czémán <barnabas.czeman@mainlining.org>
Reviewed-by: Dmitry Baryshkov <dmitry.baryshkov@linaro.org>
Reviewed-by: Christopher Obbard <christopher.obbard@linaro.org>
Tested-by: Christopher Obbard <christopher.obbard@linaro.org>
Link: https://lore.kernel.org/r/20241006-fix-postdiv-mask-v3-1-160354980433@mainlining.org
Signed-off-by: Bjorn Andersson <andersson@kernel.org>
Diffstat (limited to 'drivers/clk/qcom/clk-alpha-pll.c')
| -rw-r--r-- | drivers/clk/qcom/clk-alpha-pll.c | 2 |
1 files changed, 1 insertions, 1 deletions
diff --git a/drivers/clk/qcom/clk-alpha-pll.c b/drivers/clk/qcom/clk-alpha-pll.c index f9105443d7db..be9bee6ab65f 100644 --- a/drivers/clk/qcom/clk-alpha-pll.c +++ b/drivers/clk/qcom/clk-alpha-pll.c @@ -40,7 +40,7 @@ #define PLL_USER_CTL(p) ((p)->offset + (p)->regs[PLL_OFF_USER_CTL]) # define PLL_POST_DIV_SHIFT 8 -# define PLL_POST_DIV_MASK(p) GENMASK((p)->width - 1, 0) +# define PLL_POST_DIV_MASK(p) GENMASK((p)->width ? (p)->width - 1 : 3, 0) # define PLL_ALPHA_MSB BIT(15) # define PLL_ALPHA_EN BIT(24) # define PLL_ALPHA_MODE BIT(25) |