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| author | Jiri Kosina <jkosina@suse.cz> | 2014-11-20 14:42:02 +0100 |
|---|---|---|
| committer | Jiri Kosina <jkosina@suse.cz> | 2014-11-20 14:42:02 +0100 |
| commit | a02001086bbfb4da35d1228bebc2f1b442db455f (patch) | |
| tree | 62ab47936cef06fd08657ca5b6cd1df98c19be57 /drivers/clk/qcom/clk-rcg.h | |
| parent | kernel: trace: fix printk message (diff) | |
| parent | Linux 3.18-rc5 (diff) | |
| download | linux-a02001086bbfb4da35d1228bebc2f1b442db455f.tar.xz linux-a02001086bbfb4da35d1228bebc2f1b442db455f.zip | |
Merge Linus' tree to be be to apply submitted patches to newer code than
current trivial.git base
Diffstat (limited to 'drivers/clk/qcom/clk-rcg.h')
| -rw-r--r-- | drivers/clk/qcom/clk-rcg.h | 6 |
1 files changed, 4 insertions, 2 deletions
diff --git a/drivers/clk/qcom/clk-rcg.h b/drivers/clk/qcom/clk-rcg.h index ba0523cefd2e..687e41f91d7c 100644 --- a/drivers/clk/qcom/clk-rcg.h +++ b/drivers/clk/qcom/clk-rcg.h @@ -103,8 +103,9 @@ extern const struct clk_ops clk_rcg_bypass_ops; * struct clk_dyn_rcg - root clock generator with glitch free mux * * @mux_sel_bit: bit to switch glitch free mux - * @ns_reg: NS register + * @ns_reg: NS0 and NS1 register * @md_reg: MD0 and MD1 register + * @bank_reg: register to XOR @mux_sel_bit into to switch glitch free mux * @mn: mn counter (banked) * @s: source selector (banked) * @freq_tbl: frequency table @@ -113,8 +114,9 @@ extern const struct clk_ops clk_rcg_bypass_ops; * */ struct clk_dyn_rcg { - u32 ns_reg; + u32 ns_reg[2]; u32 md_reg[2]; + u32 bank_reg; u8 mux_sel_bit; |