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authorStephen Boyd <sboyd@codeaurora.org>2014-01-15 19:47:22 +0100
committerMike Turquette <mturquette@linaro.org>2014-01-16 21:00:57 +0100
commit3fa2252b7a78a8057017471a28f47b306e95ee26 (patch)
treee3cf04e4099a9414b15d27f6428f7726f29d7a05 /drivers/clk/qcom/clk-regmap.c
parentreset: Silence warning in reset-controller.h (diff)
downloadlinux-3fa2252b7a78a8057017471a28f47b306e95ee26.tar.xz
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clk: Add set_rate_and_parent() op
Some of Qualcomm's clocks can change their parent and rate at the same time with a single register write. Add support for this hardware to the common clock framework by adding a new set_rate_and_parent() op. When the clock framework determines that both the parent and the rate are going to change during clk_set_rate() it will call the .set_rate_and_parent() op if available and fall back to calling .set_parent() followed by .set_rate() otherwise. Reviewed-by: James Hogan <james.hogan@imgtec.com> Signed-off-by: Stephen Boyd <sboyd@codeaurora.org> Signed-off-by: Mike Turquette <mturquette@linaro.org>
Diffstat (limited to 'drivers/clk/qcom/clk-regmap.c')
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