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| author | Rajendra Nayak <rnayak@codeaurora.org> | 2016-11-18 13:28:26 +0100 |
|---|---|---|
| committer | Stephen Boyd <sboyd@codeaurora.org> | 2016-11-24 01:41:15 +0100 |
| commit | 904bb4f5c7de2f40ff31d43d3547d40910e46640 (patch) | |
| tree | 5268fb9049fcf4576592d6e800c83ecd249bc870 /drivers/clk/qcom/gdsc.h | |
| parent | Merge branch 'clk-fixes' into clk-next (diff) | |
| download | linux-904bb4f5c7de2f40ff31d43d3547d40910e46640.tar.xz linux-904bb4f5c7de2f40ff31d43d3547d40910e46640.zip | |
clk: qcom: gdsc: Add support for gdscs with HW control
Some GDSCs might support a HW control mode, where in the power
domain (gdsc) is brought in and out of low power state (while
unsued) without any SW assistance, saving power.
Such GDSCs can be configured in a HW control mode when powered on
until they are explicitly requested to be powered off by software.
Signed-off-by: Rajendra Nayak <rnayak@codeaurora.org>
Signed-off-by: Sricharan R <sricharan@codeaurora.org>
Signed-off-by: Stephen Boyd <sboyd@codeaurora.org>
Diffstat (limited to '')
| -rw-r--r-- | drivers/clk/qcom/gdsc.h | 1 |
1 files changed, 1 insertions, 0 deletions
diff --git a/drivers/clk/qcom/gdsc.h b/drivers/clk/qcom/gdsc.h index f011c4957527..39648348e5ec 100644 --- a/drivers/clk/qcom/gdsc.h +++ b/drivers/clk/qcom/gdsc.h @@ -52,6 +52,7 @@ struct gdsc { const u8 flags; #define VOTABLE BIT(0) #define CLAMP_IO BIT(1) +#define HW_CTRL BIT(2) struct reset_controller_dev *rcdev; unsigned int *resets; unsigned int reset_count; |