diff options
| author | Stephen Boyd <sboyd@codeaurora.org> | 2014-07-11 21:55:27 +0200 |
|---|---|---|
| committer | Stephen Boyd <sboyd@codeaurora.org> | 2014-07-16 01:38:59 +0200 |
| commit | 404c1ff67d241e8503fd46a09d324343aa321a8a (patch) | |
| tree | ef9e18a1029de024540d02550d1a99d162d164a1 /drivers/clk/qcom/mmcc-msm8960.c | |
| parent | clk: qcom: Add support for IPQ8064's global clock controller (GCC) (diff) | |
| download | linux-404c1ff67d241e8503fd46a09d324343aa321a8a.tar.xz linux-404c1ff67d241e8503fd46a09d324343aa321a8a.zip | |
clk: qcom: Support bypass RCG configuration
In the case of HDMI clocks, we want to bypass the RCG's ability
to divide the output clock and pass through the parent HDMI PLL
rate. Add a simple set of clk_ops to configure the RCG to do
this. This removes the need to keep adding more frequency entries
to the tv_src clock whenever we want to support a new rate.
Tested-by: Rob Clark <robdclark@gmail.com>
Signed-off-by: Stephen Boyd <sboyd@codeaurora.org>
Diffstat (limited to 'drivers/clk/qcom/mmcc-msm8960.c')
| -rw-r--r-- | drivers/clk/qcom/mmcc-msm8960.c | 9 |
1 files changed, 2 insertions, 7 deletions
diff --git a/drivers/clk/qcom/mmcc-msm8960.c b/drivers/clk/qcom/mmcc-msm8960.c index 12f3c0b64fcd..14eeeba005f3 100644 --- a/drivers/clk/qcom/mmcc-msm8960.c +++ b/drivers/clk/qcom/mmcc-msm8960.c @@ -1218,12 +1218,7 @@ static const char *mmcc_pxo_hdmi[] = { }; static struct freq_tbl clk_tbl_tv[] = { - { 25200000, P_HDMI_PLL, 1, 0, 0 }, - { 27000000, P_HDMI_PLL, 1, 0, 0 }, - { 27030000, P_HDMI_PLL, 1, 0, 0 }, - { 74250000, P_HDMI_PLL, 1, 0, 0 }, - { 108000000, P_HDMI_PLL, 1, 0, 0 }, - { 148500000, P_HDMI_PLL, 1, 0, 0 }, + { .src = P_HDMI_PLL, .pre_div = 1 }, { } }; @@ -1254,7 +1249,7 @@ static struct clk_rcg tv_src = { .name = "tv_src", .parent_names = mmcc_pxo_hdmi, .num_parents = 2, - .ops = &clk_rcg_ops, + .ops = &clk_rcg_bypass_ops, .flags = CLK_SET_RATE_PARENT, }, }, |