diff options
| author | Kumar Gala <galak@codeaurora.org> | 2014-04-04 18:32:56 +0200 |
|---|---|---|
| committer | Mike Turquette <mturquette@linaro.org> | 2014-04-30 20:54:16 +0200 |
| commit | 2c07e3c7dd487fa40983aa20704b2755c9aac477 (patch) | |
| tree | 7937aae433ff41ade2beaf679d1afefaa2e9e6ff /drivers/clk/qcom | |
| parent | clk: qcom: Add basic support for APQ8064 global clock controller clocks (diff) | |
| download | linux-2c07e3c7dd487fa40983aa20704b2755c9aac477.tar.xz linux-2c07e3c7dd487fa40983aa20704b2755c9aac477.zip | |
clk: qcom: Various fixes for MSM8960's global clock controller
* Remove CE2_SLEEP_CLK, doesn't exist on 8960 family SoCs
* Fix incorrect offset for PMIC_SSBI2_RESET
* Fix typo:
SIC_TIC -> SPS_TIC_H
SFAB_ADM0_M2_A_CLK -> SFAB_ADM0_M2_H_CLK
* Fix naming convention:
SFAB_CFPB_S_HCLK -> SFAB_CFPB_S_H_CLK
SATA_SRC_CLK -> SATA_CLK_SRC
Signed-off-by: Kumar Gala <galak@codeaurora.org>
Reviewed-by: Stephen Boyd <sboyd@codeaurora.org>
Signed-off-by: Mike Turquette <mturquette@linaro.org>
Diffstat (limited to 'drivers/clk/qcom')
| -rw-r--r-- | drivers/clk/qcom/gcc-msm8960.c | 4 |
1 files changed, 2 insertions, 2 deletions
diff --git a/drivers/clk/qcom/gcc-msm8960.c b/drivers/clk/qcom/gcc-msm8960.c index 8e2b6ddcb8e4..f4ffd91901f8 100644 --- a/drivers/clk/qcom/gcc-msm8960.c +++ b/drivers/clk/qcom/gcc-msm8960.c @@ -2810,7 +2810,7 @@ static const struct qcom_reset_map gcc_msm8960_resets[] = { [PPSS_PROC_RESET] = { 0x2594, 1 }, [PPSS_RESET] = { 0x2594}, [DMA_BAM_RESET] = { 0x25c0, 7 }, - [SIC_TIC_RESET] = { 0x2600, 7 }, + [SPS_TIC_H_RESET] = { 0x2600, 7 }, [SLIMBUS_H_RESET] = { 0x2620, 7 }, [SFAB_CFPB_M_RESET] = { 0x2680, 7 }, [SFAB_CFPB_S_RESET] = { 0x26c0, 7 }, @@ -2823,7 +2823,7 @@ static const struct qcom_reset_map gcc_msm8960_resets[] = { [SFAB_SFPB_M_RESET] = { 0x2780, 7 }, [SFAB_SFPB_S_RESET] = { 0x27a0, 7 }, [RPM_PROC_RESET] = { 0x27c0, 7 }, - [PMIC_SSBI2_RESET] = { 0x270c, 12 }, + [PMIC_SSBI2_RESET] = { 0x280c, 12 }, [SDC1_RESET] = { 0x2830 }, [SDC2_RESET] = { 0x2850 }, [SDC3_RESET] = { 0x2870 }, |