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| author | Lad Prabhakar <prabhakar.mahadev-lad.rj@bp.renesas.com> | 2021-06-09 17:32:28 +0200 |
|---|---|---|
| committer | Geert Uytterhoeven <geert+renesas@glider.be> | 2021-06-10 15:46:46 +0200 |
| commit | 17f0ff3d49ff1a9d4027f9c2bef4725ab41aa9a5 (patch) | |
| tree | 888ed51b675da2a5fef45bf8bd94e7f7ad1f9daf /drivers/clk/renesas/Makefile | |
| parent | Merge tag 'renesas-r9a07g044-dt-binding-defs-tag' into renesas-clk-for-v5.14 (diff) | |
| download | linux-17f0ff3d49ff1a9d4027f9c2bef4725ab41aa9a5.tar.xz linux-17f0ff3d49ff1a9d4027f9c2bef4725ab41aa9a5.zip | |
clk: renesas: Add support for R9A07G044 SoC
Define the clock outputs supported by RZ/G2L (R9A07G044) SoC
and bind it with RZ/G2L CPG core.
Based on a patch in the BSP by Binh Nguyen
<binh.nguyen.jz@renesas.com>.
Signed-off-by: Lad Prabhakar <prabhakar.mahadev-lad.rj@bp.renesas.com>
Reviewed-by: Biju Das <biju.das.jz@bp.renesas.com>
Link: https://lore.kernel.org/r/20210609153230.6967-10-prabhakar.mahadev-lad.rj@bp.renesas.com
Signed-off-by: Geert Uytterhoeven <geert+renesas@glider.be>
Diffstat (limited to 'drivers/clk/renesas/Makefile')
| -rw-r--r-- | drivers/clk/renesas/Makefile | 1 |
1 files changed, 1 insertions, 0 deletions
diff --git a/drivers/clk/renesas/Makefile b/drivers/clk/renesas/Makefile index a9c299686b4a..5c6c5c721d98 100644 --- a/drivers/clk/renesas/Makefile +++ b/drivers/clk/renesas/Makefile @@ -29,6 +29,7 @@ obj-$(CONFIG_CLK_R8A77990) += r8a77990-cpg-mssr.o obj-$(CONFIG_CLK_R8A77995) += r8a77995-cpg-mssr.o obj-$(CONFIG_CLK_R8A779A0) += r8a779a0-cpg-mssr.o obj-$(CONFIG_CLK_R9A06G032) += r9a06g032-clocks.o +obj-$(CONFIG_CLK_R9A07G044) += r9a07g044-cpg.o obj-$(CONFIG_CLK_SH73A0) += clk-sh73a0.o # Family |