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| author | Geert Uytterhoeven <geert+renesas@glider.be> | 2017-06-21 22:34:33 +0200 |
|---|---|---|
| committer | Geert Uytterhoeven <geert+renesas@glider.be> | 2017-10-20 11:15:37 +0200 |
| commit | 9f8c71e5134982cdf8ee35acb204715a2a47ba2e (patch) | |
| tree | 9356c9cdccacb5157196febb4146e24aa116490f /drivers/clk/renesas/clk-div6.h | |
| parent | clk: renesas: cpg-mssr: Add support to restore core clocks during resume (diff) | |
| download | linux-9f8c71e5134982cdf8ee35acb204715a2a47ba2e.tar.xz linux-9f8c71e5134982cdf8ee35acb204715a2a47ba2e.zip | |
clk: renesas: div6: Restore clock state during resume
On R-Car Gen3 systems, PSCI system suspend powers down the SoC, losing
clock configuration. Register an (optional) notifier to restore the
DIV6 clock state during system resume.
As DIV6 clocks can be picky w.r.t. modifying multiple register fields at
once, restore is not implemented by blindly restoring the register
value, but by using the existing cpg_div6_clock_{en,dis}able() helpers.
Note that this does not yet support DIV6 clocks with multiple parents,
which do not exist on R-Car Gen3 SoCs.
Signed-off-by: Geert Uytterhoeven <geert+renesas@glider.be>
Tested-by: Niklas Söderlund <niklas.soderlund+renesas@ragnatech.se>
Diffstat (limited to 'drivers/clk/renesas/clk-div6.h')
| -rw-r--r-- | drivers/clk/renesas/clk-div6.h | 3 |
1 files changed, 2 insertions, 1 deletions
diff --git a/drivers/clk/renesas/clk-div6.h b/drivers/clk/renesas/clk-div6.h index 567b31d2bfa5..da4807299dda 100644 --- a/drivers/clk/renesas/clk-div6.h +++ b/drivers/clk/renesas/clk-div6.h @@ -2,6 +2,7 @@ #define __RENESAS_CLK_DIV6_H__ struct clk *cpg_div6_register(const char *name, unsigned int num_parents, - const char **parent_names, void __iomem *reg); + const char **parent_names, void __iomem *reg, + struct raw_notifier_head *notifiers); #endif |