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| author | Rafael J. Wysocki <rafael.j.wysocki@intel.com> | 2017-01-30 09:00:02 +0100 |
|---|---|---|
| committer | Rafael J. Wysocki <rafael.j.wysocki@intel.com> | 2017-01-30 09:00:02 +0100 |
| commit | 858a0d7eb5300b5f620d98ab3c4b96c9d5f19131 (patch) | |
| tree | 79ad2ecb357183384b172155e44df71c86e24e49 /drivers/clk/renesas/clk-r8a7779.c | |
| parent | Revert "PM / sleep / ACPI: Use the ACPI_FADT_LOW_POWER_S0 flag" (diff) | |
| parent | PM / Hibernate: Use rb_entry() instead of container_of() (diff) | |
| download | linux-858a0d7eb5300b5f620d98ab3c4b96c9d5f19131.tar.xz linux-858a0d7eb5300b5f620d98ab3c4b96c9d5f19131.zip | |
Merge back earlier suspend/hibernation changes for v4.11.
Diffstat (limited to 'drivers/clk/renesas/clk-r8a7779.c')
| -rw-r--r-- | drivers/clk/renesas/clk-r8a7779.c | 18 |
1 files changed, 7 insertions, 11 deletions
diff --git a/drivers/clk/renesas/clk-r8a7779.c b/drivers/clk/renesas/clk-r8a7779.c index cf2a37df03b1..27fbfafaf2cd 100644 --- a/drivers/clk/renesas/clk-r8a7779.c +++ b/drivers/clk/renesas/clk-r8a7779.c @@ -18,6 +18,7 @@ #include <linux/of_address.h> #include <linux/slab.h> #include <linux/spinlock.h> +#include <linux/soc/renesas/rcar-rst.h> #include <dt-bindings/clock/r8a7779-clock.h> @@ -88,8 +89,6 @@ static const unsigned int cpg_plla_mult[4] __initconst = { 42, 48, 56, 64 }; * Initialization */ -static u32 cpg_mode __initdata; - static struct clk * __init r8a7779_cpg_register_clock(struct device_node *np, struct r8a7779_cpg *cpg, const struct cpg_clk_config *config, @@ -127,6 +126,10 @@ static void __init r8a7779_cpg_clocks_init(struct device_node *np) struct clk **clks; unsigned int i, plla_mult; int num_clks; + u32 mode; + + if (rcar_rst_read_mode_pins(&mode)) + return; num_clks = of_property_count_strings(np, "clock-output-names"); if (num_clks < 0) { @@ -148,8 +151,8 @@ static void __init r8a7779_cpg_clocks_init(struct device_node *np) cpg->data.clks = clks; cpg->data.clk_num = num_clks; - config = &cpg_clk_configs[CPG_CLK_CONFIG_INDEX(cpg_mode)]; - plla_mult = cpg_plla_mult[CPG_PLLA_MULT_INDEX(cpg_mode)]; + config = &cpg_clk_configs[CPG_CLK_CONFIG_INDEX(mode)]; + plla_mult = cpg_plla_mult[CPG_PLLA_MULT_INDEX(mode)]; for (i = 0; i < num_clks; ++i) { const char *name; @@ -173,10 +176,3 @@ static void __init r8a7779_cpg_clocks_init(struct device_node *np) } CLK_OF_DECLARE(r8a7779_cpg_clks, "renesas,r8a7779-cpg-clocks", r8a7779_cpg_clocks_init); - -void __init r8a7779_clocks_init(u32 mode) -{ - cpg_mode = mode; - - of_clk_init(NULL); -} |