diff options
| author | Andrey Gusakov <andrey.gusakov@cogentembedded.com> | 2021-09-29 23:34:32 +0200 |
|---|---|---|
| committer | Geert Uytterhoeven <geert+renesas@glider.be> | 2021-10-15 09:46:14 +0200 |
| commit | 2bd9feed23166f5ab67dec2ca02bd3f74c77b0ba (patch) | |
| tree | 0caf91c073ccd8c26c4b1ffce206a66aa36652e1 /drivers/clk/renesas/r8a7796-cpg-mssr.c | |
| parent | clk: renesas: r9a07g044: Add SDHI clock and reset entries (diff) | |
| download | linux-2bd9feed23166f5ab67dec2ca02bd3f74c77b0ba.tar.xz linux-2bd9feed23166f5ab67dec2ca02bd3f74c77b0ba.zip | |
clk: renesas: r8a779[56]x: Add MLP clocks
Add clocks for MLP modules on Renesas R-Car H3 and M3-W/N SoCs.
Signed-off-by: Andrey Gusakov <andrey.gusakov@cogentembedded.com>
Signed-off-by: Nikita Yushchenko <nikita.yoush@cogentembedded.com>
Link: https://lore.kernel.org/r/20210929213431.5275-1-nikita.yoush@cogentembedded.com
Signed-off-by: Geert Uytterhoeven <geert+renesas@glider.be>
Diffstat (limited to 'drivers/clk/renesas/r8a7796-cpg-mssr.c')
| -rw-r--r-- | drivers/clk/renesas/r8a7796-cpg-mssr.c | 1 |
1 files changed, 1 insertions, 0 deletions
diff --git a/drivers/clk/renesas/r8a7796-cpg-mssr.c b/drivers/clk/renesas/r8a7796-cpg-mssr.c index 41593c126faf..9c22977e42c2 100644 --- a/drivers/clk/renesas/r8a7796-cpg-mssr.c +++ b/drivers/clk/renesas/r8a7796-cpg-mssr.c @@ -207,6 +207,7 @@ static struct mssr_mod_clk r8a7796_mod_clks[] __initdata = { DEF_MOD("du0", 724, R8A7796_CLK_S2D1), DEF_MOD("lvds", 727, R8A7796_CLK_S2D1), DEF_MOD("hdmi0", 729, R8A7796_CLK_HDMI), + DEF_MOD("mlp", 802, R8A7796_CLK_S2D1), DEF_MOD("vin7", 804, R8A7796_CLK_S0D2), DEF_MOD("vin6", 805, R8A7796_CLK_S0D2), DEF_MOD("vin5", 806, R8A7796_CLK_S0D2), |