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| author | Stephen Boyd <sboyd@kernel.org> | 2018-05-16 00:36:41 +0200 |
|---|---|---|
| committer | Stephen Boyd <sboyd@kernel.org> | 2018-05-16 00:39:26 +0200 |
| commit | 402b0042071194d62132d2c69c0ddecbb5b08c84 (patch) | |
| tree | 9e035cd13a821b55329f3dad63a4a18ce1456600 /drivers/clk/renesas/r8a77965-cpg-mssr.c | |
| parent | Linux 4.17-rc1 (diff) | |
| parent | clk: renesas: cpg-mssr: Add support for R-Car E3 (diff) | |
| download | linux-402b0042071194d62132d2c69c0ddecbb5b08c84.tar.xz linux-402b0042071194d62132d2c69c0ddecbb5b08c84.zip | |
Merge tag 'clk-renesas-for-v4.18-tag1' of git://git.kernel.org/pub/scm/linux/kernel/git/geert/renesas-drivers into clk-renesas
Pull renesas clk driver updates from Geert Uytterhoeven:
- Add support for the MSIOF module clocks on R-Car M3-N
- Add support for the new RZ/G1C and R-Car E3 SoCs
* tag 'clk-renesas-for-v4.18-tag1' of git://git.kernel.org/pub/scm/linux/kernel/git/geert/renesas-drivers:
clk: renesas: cpg-mssr: Add support for R-Car E3
clk: renesas: Add r8a77990 CPG Core Clock Definitions
clk: renesas: rcar-gen2: Centralize quirks handling
clk: renesas: r8a77980: Correct parent clock of PCIEC0
clk: renesas: r8a7794: Fix LB clock divider
clk: renesas: r8a7792: Fix LB clock divider
clk: renesas: r8a7791/r8a7793: Fix LB clock divider
clk: renesas: r8a7745: Fix LB clock divider
clk: renesas: r8a7743: Fix LB clock divider
clk: renesas: cpg-mssr: Add r8a77470 support
clk: renesas: Add r8a77470 CPG Core Clock Definitions
clk: renesas: r8a77965: Add MSIOF controller clocks
Diffstat (limited to 'drivers/clk/renesas/r8a77965-cpg-mssr.c')
| -rw-r--r-- | drivers/clk/renesas/r8a77965-cpg-mssr.c | 4 |
1 files changed, 4 insertions, 0 deletions
diff --git a/drivers/clk/renesas/r8a77965-cpg-mssr.c b/drivers/clk/renesas/r8a77965-cpg-mssr.c index b1acfb60351c..8fae5e9c4a77 100644 --- a/drivers/clk/renesas/r8a77965-cpg-mssr.c +++ b/drivers/clk/renesas/r8a77965-cpg-mssr.c @@ -116,6 +116,10 @@ static const struct mssr_mod_clk r8a77965_mod_clks[] __initconst = { DEF_MOD("scif3", 204, R8A77965_CLK_S3D4), DEF_MOD("scif1", 206, R8A77965_CLK_S3D4), DEF_MOD("scif0", 207, R8A77965_CLK_S3D4), + DEF_MOD("msiof3", 208, R8A77965_CLK_MSO), + DEF_MOD("msiof2", 209, R8A77965_CLK_MSO), + DEF_MOD("msiof1", 210, R8A77965_CLK_MSO), + DEF_MOD("msiof0", 211, R8A77965_CLK_MSO), DEF_MOD("sys-dmac2", 217, R8A77965_CLK_S0D3), DEF_MOD("sys-dmac1", 218, R8A77965_CLK_S0D3), DEF_MOD("sys-dmac0", 219, R8A77965_CLK_S0D3), |