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| author | Geert Uytterhoeven <geert+renesas@glider.be> | 2021-07-14 15:26:01 +0200 |
|---|---|---|
| committer | Geert Uytterhoeven <geert+renesas@glider.be> | 2021-07-19 11:22:20 +0200 |
| commit | 0aae437ac5c264e8e2cb6c3fead20b44d2fa31d1 (patch) | |
| tree | 94cb249e636b0e8845fa20535dec1a4a12460690 /drivers/clk/renesas/r9a07g044-cpg.c | |
| parent | clk: renesas: r9a07g044: Add GPIO clock and reset entries (diff) | |
| download | linux-0aae437ac5c264e8e2cb6c3fead20b44d2fa31d1.tar.xz linux-0aae437ac5c264e8e2cb6c3fead20b44d2fa31d1.zip | |
clk: renesas: Rename renesas-rzg2l-cpg.[ch] to rzg2l-cpg.[ch]
Rename renesas-rzg2l-cpg.c and renesas-rzg2l-cpg.h to rzg2l-cpg.c resp.
rzg2l-cpg.h, for consistency with other (sub)drivers.
Signed-off-by: Geert Uytterhoeven <geert+renesas@glider.be>
Reviewed-by: Lad Prabhakar <prabhakar.mahadev-lad.rj@bp.renesas.com>
Acked-by: Biju Das <biju.das.jz@bp.renesas.com>
Link: https://lore.kernel.org/r/edc442daaedffcf10e835ff479d906fcae0e59db.1626268821.git.geert+renesas@glider.be
Diffstat (limited to 'drivers/clk/renesas/r9a07g044-cpg.c')
| -rw-r--r-- | drivers/clk/renesas/r9a07g044-cpg.c | 2 |
1 files changed, 1 insertions, 1 deletions
diff --git a/drivers/clk/renesas/r9a07g044-cpg.c b/drivers/clk/renesas/r9a07g044-cpg.c index 78fae93cf249..6a1d9532a690 100644 --- a/drivers/clk/renesas/r9a07g044-cpg.c +++ b/drivers/clk/renesas/r9a07g044-cpg.c @@ -12,7 +12,7 @@ #include <dt-bindings/clock/r9a07g044-cpg.h> -#include "renesas-rzg2l-cpg.h" +#include "rzg2l-cpg.h" enum clk_ids { /* Core Clock Outputs exported to DT */ |