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| author | Fabrizio Castro <fabrizio.castro@bp.renesas.com> | 2018-09-12 12:41:53 +0200 |
|---|---|---|
| committer | Geert Uytterhoeven <geert+renesas@glider.be> | 2018-09-19 16:42:14 +0200 |
| commit | 906e0a4a6d1ef2d3940cd7f17287b111730382da (patch) | |
| tree | 3079cd1e2ae2b2ce6ff5ef652e922e92f1a69d8e /drivers/clk/renesas/rcar-gen3-cpg.c | |
| parent | clk: renesas: Add r8a774c0 CPG Core Clock Definitions (diff) | |
| download | linux-906e0a4a6d1ef2d3940cd7f17287b111730382da.tar.xz linux-906e0a4a6d1ef2d3940cd7f17287b111730382da.zip | |
clk: renesas: cpg-mssr: Add r8a774c0 support
Add RZ/G2E (R8A774C0) Clock Pulse Generator / Module Standby and
Software Reset support.
Based on Table 8.2g of "RZ/G Series, 2nd Generation User's Manual:
Hardware (Rev. 0.61, June 12, 2018)".
Signed-off-by: Fabrizio Castro <fabrizio.castro@bp.renesas.com>
Reviewed-by: Biju Das <biju.das@bp.renesas.com>
Signed-off-by: Geert Uytterhoeven <geert+renesas@glider.be>
Diffstat (limited to 'drivers/clk/renesas/rcar-gen3-cpg.c')
0 files changed, 0 insertions, 0 deletions