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authorGeert Uytterhoeven <geert+renesas@glider.be>2018-03-15 10:44:37 +0100
committerGeert Uytterhoeven <geert+renesas@glider.be>2018-03-21 17:35:00 +0100
commit2b935d524d851830b68dd8c58d3098d775d6047a (patch)
tree3a610ea9b6cf5ba661622072d55ec62a444c5551 /drivers/clk/renesas/renesas-cpg-mssr.c
parentclk: renesas: sh73a0: Always use readl()/writel() (diff)
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clk: renesas: rcar-gen3: Always use readl()/writel()
The R-Car Gen3 CPG/MSSR driver (again) uses a mix of clk_readl()/clk_writel() and readl()/writel() to access the clock registers. Settle on the generic readl()/writel(). Cfr. commit 30ad3cf00e94f4a7 ("clk: renesas: rcar-gen3-cpg: Always use readl()/writel()"). Signed-off-by: Geert Uytterhoeven <geert+renesas@glider.be> Reviewed-by: Simon Horman <horms+renesas@verge.net.au>
Diffstat (limited to 'drivers/clk/renesas/renesas-cpg-mssr.c')
0 files changed, 0 insertions, 0 deletions