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| author | Wolfram Sang <wsa+renesas@sang-engineering.com> | 2016-03-30 16:58:19 +0200 |
|---|---|---|
| committer | Geert Uytterhoeven <geert+renesas@glider.be> | 2016-04-06 09:48:44 +0200 |
| commit | 5524a67f3a4ad8625cab6a9b99419f747cea4c71 (patch) | |
| tree | d76ef60b2d40f5897debb7df022d0d913ce31f64 /drivers/clk/renesas | |
| parent | clk: renesas: cpg-mssr: add generic support for read-only DIV6 clocks (diff) | |
| download | linux-5524a67f3a4ad8625cab6a9b99419f747cea4c71.tar.xz linux-5524a67f3a4ad8625cab6a9b99419f747cea4c71.zip | |
clk: renesas: r8a7795: add OSC and RINT clocks
Signed-off-by: Wolfram Sang <wsa+renesas@sang-engineering.com>
Signed-off-by: Geert Uytterhoeven <geert+renesas@glider.be>
Diffstat (limited to 'drivers/clk/renesas')
| -rw-r--r-- | drivers/clk/renesas/r8a7795-cpg-mssr.c | 5 |
1 files changed, 5 insertions, 0 deletions
diff --git a/drivers/clk/renesas/r8a7795-cpg-mssr.c b/drivers/clk/renesas/r8a7795-cpg-mssr.c index 9dc2b735ead8..08715ca2ebb4 100644 --- a/drivers/clk/renesas/r8a7795-cpg-mssr.c +++ b/drivers/clk/renesas/r8a7795-cpg-mssr.c @@ -26,6 +26,7 @@ #include "renesas-cpg-mssr.h" +#define CPG_RCKCR 0x240 enum clk_ids { /* Core Clock Outputs exported to DT */ @@ -50,6 +51,7 @@ enum clk_ids { CLK_S3, CLK_SDSRC, CLK_SSPSRC, + CLK_RINT, /* Module Clocks */ MOD_CLK_BASE @@ -116,6 +118,9 @@ static const struct cpg_core_clk r8a7795_core_clks[] __initconst = { DEF_DIV6P1("mso", R8A7795_CLK_MSO, CLK_PLL1_DIV4, 0x014), DEF_DIV6P1("hdmi", R8A7795_CLK_HDMI, CLK_PLL1_DIV2, 0x250), DEF_DIV6P1("canfd", R8A7795_CLK_CANFD, CLK_PLL1_DIV4, 0x244), + + DEF_DIV6_RO("osc", R8A7795_CLK_OSC, CLK_EXTAL, CPG_RCKCR, 8), + DEF_DIV6_RO("r_int", CLK_RINT, CLK_EXTAL, CPG_RCKCR, 32), }; static const struct mssr_mod_clk r8a7795_mod_clks[] __initconst = { |