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| author | Chris Brandt <chris.brandt@renesas.com> | 2018-10-08 18:23:47 +0200 |
|---|---|---|
| committer | Geert Uytterhoeven <geert+renesas@glider.be> | 2018-11-05 13:59:34 +0100 |
| commit | 507c93a22c84209469fb03238ccdc5da3c6417fc (patch) | |
| tree | b9fee7be01f92fb010c636e65111c6088b8807b3 /drivers/clk/renesas | |
| parent | Linux 4.20-rc1 (diff) | |
| download | linux-507c93a22c84209469fb03238ccdc5da3c6417fc.tar.xz linux-507c93a22c84209469fb03238ccdc5da3c6417fc.zip | |
clk: renesas: r7s9210: Add SDHI clocks
Add SDHI clocks for RZ/A2
Signed-off-by: Chris Brandt <chris.brandt@renesas.com>
Signed-off-by: Geert Uytterhoeven <geert+renesas@glider.be>
Diffstat (limited to 'drivers/clk/renesas')
| -rw-r--r-- | drivers/clk/renesas/r7s9210-cpg-mssr.c | 5 |
1 files changed, 5 insertions, 0 deletions
diff --git a/drivers/clk/renesas/r7s9210-cpg-mssr.c b/drivers/clk/renesas/r7s9210-cpg-mssr.c index 5135f13ec628..9056da15dc72 100644 --- a/drivers/clk/renesas/r7s9210-cpg-mssr.c +++ b/drivers/clk/renesas/r7s9210-cpg-mssr.c @@ -98,6 +98,11 @@ static const struct mssr_mod_clk r7s9210_mod_clks[] __initconst = { DEF_MOD_STB("spi2", 95, R7S9210_CLK_P1), DEF_MOD_STB("spi1", 96, R7S9210_CLK_P1), DEF_MOD_STB("spi0", 97, R7S9210_CLK_P1), + + DEF_MOD_STB("sdhi11", 100, R7S9210_CLK_B), + DEF_MOD_STB("sdhi10", 101, R7S9210_CLK_B), + DEF_MOD_STB("sdhi01", 102, R7S9210_CLK_B), + DEF_MOD_STB("sdhi00", 103, R7S9210_CLK_B), }; /* The clock dividers in the table vary based on DT and register settings */ |