diff options
| author | Biju Das <biju.das.jz@bp.renesas.com> | 2022-04-25 11:52:39 +0200 |
|---|---|---|
| committer | Geert Uytterhoeven <geert+renesas@glider.be> | 2022-04-28 16:37:44 +0200 |
| commit | a9391e019015e96d4ed40587ce0f648edf1c32d3 (patch) | |
| tree | 0201feeb7bc527a3ce4e74e0a0fc6cb29c3b67a1 /drivers/clk/renesas | |
| parent | clk: renesas: r9a06g032: Fix the RTC hclock description (diff) | |
| download | linux-a9391e019015e96d4ed40587ce0f648edf1c32d3.tar.xz linux-a9391e019015e96d4ed40587ce0f648edf1c32d3.zip | |
clk: renesas: r9a07g043: Add I2C clocks/resets
Add I2C{0,1,2,3} clock and reset entries.
Signed-off-by: Biju Das <biju.das.jz@bp.renesas.com>
Link: https://lore.kernel.org/r/20220425095244.156720-2-biju.das.jz@bp.renesas.com
Signed-off-by: Geert Uytterhoeven <geert+renesas@glider.be>
Diffstat (limited to 'drivers/clk/renesas')
| -rw-r--r-- | drivers/clk/renesas/r9a07g043-cpg.c | 12 |
1 files changed, 12 insertions, 0 deletions
diff --git a/drivers/clk/renesas/r9a07g043-cpg.c b/drivers/clk/renesas/r9a07g043-cpg.c index 2d6c96789f5c..961216d55e0b 100644 --- a/drivers/clk/renesas/r9a07g043-cpg.c +++ b/drivers/clk/renesas/r9a07g043-cpg.c @@ -152,6 +152,14 @@ static struct rzg2l_mod_clk r9a07g043_mod_clks[] = { 0x57c, 1), DEF_COUPLED("eth1_chi", R9A07G043_ETH1_CLK_CHI, R9A07G043_CLK_ZT, 0x57c, 1), + DEF_MOD("i2c0", R9A07G043_I2C0_PCLK, R9A07G043_CLK_P0, + 0x580, 0), + DEF_MOD("i2c1", R9A07G043_I2C1_PCLK, R9A07G043_CLK_P0, + 0x580, 1), + DEF_MOD("i2c2", R9A07G043_I2C2_PCLK, R9A07G043_CLK_P0, + 0x580, 2), + DEF_MOD("i2c3", R9A07G043_I2C3_PCLK, R9A07G043_CLK_P0, + 0x580, 3), DEF_MOD("scif0", R9A07G043_SCIF0_CLK_PCK, R9A07G043_CLK_P0, 0x584, 0), DEF_MOD("scif1", R9A07G043_SCIF1_CLK_PCK, R9A07G043_CLK_P0, @@ -180,6 +188,10 @@ static struct rzg2l_reset r9a07g043_resets[] = { DEF_RST(R9A07G043_SDHI1_IXRST, 0x854, 1), DEF_RST(R9A07G043_ETH0_RST_HW_N, 0x87c, 0), DEF_RST(R9A07G043_ETH1_RST_HW_N, 0x87c, 1), + DEF_RST(R9A07G043_I2C0_MRST, 0x880, 0), + DEF_RST(R9A07G043_I2C1_MRST, 0x880, 1), + DEF_RST(R9A07G043_I2C2_MRST, 0x880, 2), + DEF_RST(R9A07G043_I2C3_MRST, 0x880, 3), DEF_RST(R9A07G043_SCIF0_RST_SYSTEM_N, 0x884, 0), DEF_RST(R9A07G043_SCIF1_RST_SYSTEM_N, 0x884, 1), DEF_RST(R9A07G043_SCIF2_RST_SYSTEM_N, 0x884, 2), |