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| author | Lad Prabhakar <prabhakar.mahadev-lad.rj@bp.renesas.com> | 2021-07-12 21:44:20 +0200 |
|---|---|---|
| committer | Geert Uytterhoeven <geert+renesas@glider.be> | 2021-07-19 11:22:10 +0200 |
| commit | d85b82f09a03c2e1f06da740c6c47dd098b16ca5 (patch) | |
| tree | 4ddd884442b1168e5abb05ebc60a4cc4db6d6021 /drivers/clk/renesas | |
| parent | clk: renesas: r9a07g044: Add SSIF-2 clock and reset entries (diff) | |
| download | linux-d85b82f09a03c2e1f06da740c6c47dd098b16ca5.tar.xz linux-d85b82f09a03c2e1f06da740c6c47dd098b16ca5.zip | |
clk: renesas: r9a07g044: Add GPIO clock and reset entries
Add GPIO clock and reset entries in CPG driver.
Signed-off-by: Lad Prabhakar <prabhakar.mahadev-lad.rj@bp.renesas.com>
Reviewed-by: Biju Das <biju.das.jz@bp.renesas.com>
Link: https://lore.kernel.org/r/20210712194422.12405-4-prabhakar.mahadev-lad.rj@bp.renesas.com
Signed-off-by: Geert Uytterhoeven <geert+renesas@glider.be>
Diffstat (limited to 'drivers/clk/renesas')
| -rw-r--r-- | drivers/clk/renesas/r9a07g044-cpg.c | 5 |
1 files changed, 5 insertions, 0 deletions
diff --git a/drivers/clk/renesas/r9a07g044-cpg.c b/drivers/clk/renesas/r9a07g044-cpg.c index ed5f5c11ac12..78fae93cf249 100644 --- a/drivers/clk/renesas/r9a07g044-cpg.c +++ b/drivers/clk/renesas/r9a07g044-cpg.c @@ -140,6 +140,8 @@ static struct rzg2l_mod_clk r9a07g044_mod_clks[] = { 0x584, 4), DEF_MOD("sci0", R9A07G044_SCI0_CLKP, R9A07G044_CLK_P0, 0x588, 0), + DEF_MOD("gpio", R9A07G044_GPIO_HCLK, R9A07G044_OSCCLK, + 0x598, 0), }; static struct rzg2l_reset r9a07g044_resets[] = { @@ -166,6 +168,9 @@ static struct rzg2l_reset r9a07g044_resets[] = { DEF_RST(R9A07G044_SCIF3_RST_SYSTEM_N, 0x884, 3), DEF_RST(R9A07G044_SCIF4_RST_SYSTEM_N, 0x884, 4), DEF_RST(R9A07G044_SCI0_RST, 0x888, 0), + DEF_RST(R9A07G044_GPIO_RSTN, 0x898, 0), + DEF_RST(R9A07G044_GPIO_PORT_RESETN, 0x898, 1), + DEF_RST(R9A07G044_GPIO_SPARE_RESETN, 0x898, 2), }; static const unsigned int r9a07g044_crit_mod_clks[] __initconst = { |