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authorElaine Zhang <zhangqing@rock-chips.com>2016-12-29 03:45:10 +0100
committerHeiko Stuebner <heiko@sntech.de>2017-01-02 14:24:57 +0100
commit7bed92460d910c75f0d722f1240d2dc1d466d884 (patch)
treebd93e4e945478ec6a7806d1856788dd5b2ae8d33 /drivers/clk/rockchip/clk-rk3368.c
parentclk: rockchip: describe aclk_vcodec using the new muxgrf type on rk3288 (diff)
downloadlinux-7bed92460d910c75f0d722f1240d2dc1d466d884.tar.xz
linux-7bed92460d910c75f0d722f1240d2dc1d466d884.zip
clk: rockchip: add new pll-type for rk3328
The rk3328's pll and clock are similar with rk3036's, it different with pll_mode_mask, the rk3328 soc pll mode only one bit(rk3036 soc have two bits) so these should be independent and separate from the series of rk3328s. Signed-off-by: Elaine Zhang <zhangqing@rock-chips.com> Signed-off-by: Heiko Stuebner <heiko@sntech.de>
Diffstat (limited to 'drivers/clk/rockchip/clk-rk3368.c')
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