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authorHeiko Stuebner <heiko@sntech.de>2014-11-20 20:38:50 +0100
committerHeiko Stuebner <heiko@sntech.de>2014-11-25 09:57:07 +0100
commit4f8a7c549f373f33c065c9cbb5a5f3f1a9d8f56c (patch)
tree6c3adc9b74f0663ec871a0cc45309b7044657d68 /drivers/clk/rockchip/clk.c
parentclk: rockchip: fix rk3188 USB HSIC PHY clock divider (diff)
downloadlinux-4f8a7c549f373f33c065c9cbb5a5f3f1a9d8f56c.tar.xz
linux-4f8a7c549f373f33c065c9cbb5a5f3f1a9d8f56c.zip
clk: rockchip: add ability to specify pll-specific flags
This adds a flag parameter to plls that allows us to create special flags to tweak the behaviour of the plls if necessary. Signed-off-by: Heiko Stuebner <heiko@sntech.de> Reviewed-by: Kever Yang <kever.yang@rock-chips.com> Tested-by: Kever Yang <kever.yang@rock-chips.com>
Diffstat (limited to 'drivers/clk/rockchip/clk.c')
-rw-r--r--drivers/clk/rockchip/clk.c3
1 files changed, 2 insertions, 1 deletions
diff --git a/drivers/clk/rockchip/clk.c b/drivers/clk/rockchip/clk.c
index dec6f8d6dc13..3b8f26e2cd1a 100644
--- a/drivers/clk/rockchip/clk.c
+++ b/drivers/clk/rockchip/clk.c
@@ -199,7 +199,8 @@ void __init rockchip_clk_register_plls(struct rockchip_pll_clock *list,
list->parent_names, list->num_parents,
reg_base, list->con_offset, grf_lock_offset,
list->lock_shift, list->mode_offset,
- list->mode_shift, list->rate_table, &clk_lock);
+ list->mode_shift, list->rate_table,
+ list->pll_flags, &clk_lock);
if (IS_ERR(clk)) {
pr_err("%s: failed to register clock %s\n", __func__,
list->name);