diff options
| author | Elaine Zhang <zhangqing@rock-chips.com> | 2016-12-29 03:45:11 +0100 |
|---|---|---|
| committer | Heiko Stuebner <heiko@sntech.de> | 2017-01-05 13:36:07 +0100 |
| commit | fe3511ad8a1cf63721f5f3e64996e16006e1d7d2 (patch) | |
| tree | a09096d3b0b36984c84094de427d8d34942e84a0 /drivers/clk/rockchip/clk.h | |
| parent | dt-bindings: add bindings for rk3328 clock controller (diff) | |
| download | linux-fe3511ad8a1cf63721f5f3e64996e16006e1d7d2.tar.xz linux-fe3511ad8a1cf63721f5f3e64996e16006e1d7d2.zip | |
clk: rockchip: add clock controller for rk3328
Add the clock tree definition for the new rk3328 SoC.
Signed-off-by: Elaine Zhang <zhangqing@rock-chips.com>
Signed-off-by: Heiko Stuebner <heiko@sntech.de>
Diffstat (limited to 'drivers/clk/rockchip/clk.h')
| -rw-r--r-- | drivers/clk/rockchip/clk.h | 18 |
1 files changed, 18 insertions, 0 deletions
diff --git a/drivers/clk/rockchip/clk.h b/drivers/clk/rockchip/clk.h index 8f83cde407c9..7c15473ea72b 100644 --- a/drivers/clk/rockchip/clk.h +++ b/drivers/clk/rockchip/clk.h @@ -91,6 +91,24 @@ struct clk; #define RK3288_EMMC_CON0 0x218 #define RK3288_EMMC_CON1 0x21c +#define RK3328_PLL_CON(x) RK2928_PLL_CON(x) +#define RK3328_CLKSEL_CON(x) ((x) * 0x4 + 0x100) +#define RK3328_CLKGATE_CON(x) ((x) * 0x4 + 0x200) +#define RK3328_GRFCLKSEL_CON(x) ((x) * 0x4 + 0x100) +#define RK3328_GLB_SRST_FST 0x9c +#define RK3328_GLB_SRST_SND 0x98 +#define RK3328_SOFTRST_CON(x) ((x) * 0x4 + 0x300) +#define RK3328_MODE_CON 0x80 +#define RK3328_MISC_CON 0x84 +#define RK3328_SDMMC_CON0 0x380 +#define RK3328_SDMMC_CON1 0x384 +#define RK3328_SDIO_CON0 0x388 +#define RK3328_SDIO_CON1 0x38c +#define RK3328_EMMC_CON0 0x390 +#define RK3328_EMMC_CON1 0x394 +#define RK3328_SDMMC_EXT_CON0 0x398 +#define RK3328_SDMMC_EXT_CON1 0x39C + #define RK3368_PLL_CON(x) RK2928_PLL_CON(x) #define RK3368_CLKSEL_CON(x) ((x) * 0x4 + 0x100) #define RK3368_CLKGATE_CON(x) ((x) * 0x4 + 0x200) |