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authorJeffy Chen <jeffy.chen@rock-chips.com>2015-12-11 02:30:50 +0100
committerHeiko Stuebner <heiko@sntech.de>2015-12-12 20:04:54 +0100
commit307a2e9ac524bbec707c0e2b47ca50adaecc23f2 (patch)
tree39420e03b8c079069f98d7d42fa6d8fd234ffe17 /drivers/clk/rockchip/clk.h
parentdt-bindings: add documentation of rk3228 clock controller (diff)
downloadlinux-307a2e9ac524bbec707c0e2b47ca50adaecc23f2.tar.xz
linux-307a2e9ac524bbec707c0e2b47ca50adaecc23f2.zip
clk: rockchip: add clock controller for rk3228
Add the clock tree definition for the new rk3228 SoC. Signed-off-by: Jeffy Chen <jeffy.chen@rock-chips.com> Signed-off-by: Heiko Stuebner <heiko@sntech.de>
Diffstat (limited to 'drivers/clk/rockchip/clk.h')
-rw-r--r--drivers/clk/rockchip/clk.h11
1 files changed, 10 insertions, 1 deletions
diff --git a/drivers/clk/rockchip/clk.h b/drivers/clk/rockchip/clk.h
index 8d8f942ae7fc..01bc372bb048 100644
--- a/drivers/clk/rockchip/clk.h
+++ b/drivers/clk/rockchip/clk.h
@@ -33,7 +33,7 @@ struct clk;
#define HIWORD_UPDATE(val, mask, shift) \
((val) << (shift) | (mask) << ((shift) + 16))
-/* register positions shared by RK2928, RK3036, RK3066 and RK3188 */
+/* register positions shared by RK2928, RK3036, RK3066, RK3188 and RK3228 */
#define RK2928_PLL_CON(x) ((x) * 0x4)
#define RK2928_MODE_CON 0x40
#define RK2928_CLKSEL_CON(x) ((x) * 0x4 + 0x44)
@@ -50,6 +50,15 @@ struct clk;
#define RK3036_EMMC_CON0 0x154
#define RK3036_EMMC_CON1 0x158
+#define RK3228_GLB_SRST_FST 0x1f0
+#define RK3228_GLB_SRST_SND 0x1f4
+#define RK3228_SDMMC_CON0 0x1c0
+#define RK3228_SDMMC_CON1 0x1c4
+#define RK3228_SDIO_CON0 0x1c8
+#define RK3228_SDIO_CON1 0x1cc
+#define RK3228_EMMC_CON0 0x1d8
+#define RK3228_EMMC_CON1 0x1dc
+
#define RK3288_PLL_CON(x) RK2928_PLL_CON(x)
#define RK3288_MODE_CON 0x50
#define RK3288_CLKSEL_CON(x) ((x) * 0x4 + 0x60)