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| author | Tony Lindgren <tony@atomide.com> | 2015-03-17 02:04:20 +0100 |
|---|---|---|
| committer | Tero Kristo <t-kristo@ti.com> | 2015-03-24 19:26:05 +0100 |
| commit | cafeb002cf2cd8b0f8796b59130f9c1b91da4fcf (patch) | |
| tree | 0f957ea927d32ea9691dee48a663581d7ca341c3 /drivers/clk/samsung/clk-exynos-audss.c | |
| parent | clk: ti: Fix FAPLL recalc_rate for rounding errors (diff) | |
| download | linux-cafeb002cf2cd8b0f8796b59130f9c1b91da4fcf.tar.xz linux-cafeb002cf2cd8b0f8796b59130f9c1b91da4fcf.zip | |
clk: ti: Implement FAPLL set_rate for the synthesizer
We can pretty much get any rate out of the FAPLL because of the fractional
divider. Let's first try just adjusting the post divider, and if that is
not enough, then reprogram both the fractional divider and the post divider.
Let's also add a define for the fixed SYNTH_PHASE_K instead of using 8.
Cc: Brian Hutchinson <b.hutchman@gmail.com>
Cc: Matthijs van Duin <matthijsvanduin@gmail.com>
Cc: Tero Kristo <t-kristo@ti.com>
Signed-off-by: Tony Lindgren <tony@atomide.com>
Signed-off-by: Tero Kristo <t-kristo@ti.com>
Diffstat (limited to 'drivers/clk/samsung/clk-exynos-audss.c')
0 files changed, 0 insertions, 0 deletions