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authorTomasz Figa <t.figa@samsung.com>2013-04-04 06:32:51 +0200
committerKukjin Kim <kgene.kim@samsung.com>2013-04-04 08:51:08 +0200
commit6976d27415a10d19a718a2e4f862f5c5cc25fd19 (patch)
tree8b383acfcba419beeb3187945bdc49bd6ce04447 /drivers/clk/samsung/clk-exynos4.c
parentclk: exynos4: Add missing sclk_audio0 clock (diff)
downloadlinux-6976d27415a10d19a718a2e4f862f5c5cc25fd19.tar.xz
linux-6976d27415a10d19a718a2e4f862f5c5cc25fd19.zip
clk: exynos4: Export sclk_pcm0
This clock is used by PCM interface 0. Signed-off-by: Tomasz Figa <t.figa@samsung.com> Signed-off-by: Kyungmin Park <kyungmin.park@samsung.com> Reviewed-by: Thomas Abraham <thomas.abraham@linaro.org> Acked-by: Mike Turquette <mturquette@linaro.org> Signed-off-by: Kukjin Kim <kgene.kim@samsung.com>
Diffstat (limited to 'drivers/clk/samsung/clk-exynos4.c')
-rw-r--r--drivers/clk/samsung/clk-exynos4.c4
1 files changed, 2 insertions, 2 deletions
diff --git a/drivers/clk/samsung/clk-exynos4.c b/drivers/clk/samsung/clk-exynos4.c
index 0e89d97c2ce3..96f2e746473d 100644
--- a/drivers/clk/samsung/clk-exynos4.c
+++ b/drivers/clk/samsung/clk-exynos4.c
@@ -122,7 +122,7 @@ enum exynos4_clks {
sclk_sata, sclk_uart0, sclk_uart1, sclk_uart2, sclk_uart3, sclk_uart4,
sclk_audio1, sclk_audio2, sclk_spdif, sclk_spi0, sclk_spi1, sclk_spi2,
sclk_slimbus, sclk_fimd1, sclk_mipi1, sclk_pcm1, sclk_pcm2, sclk_i2s1,
- sclk_i2s2, sclk_mipihsi, sclk_mfc,
+ sclk_i2s2, sclk_mipihsi, sclk_mfc, sclk_pcm0,
/* gate clocks */
fimc0 = 256, fimc1, fimc2, fimc3, csis0, csis1, jpeg, smmu_fimc0,
@@ -411,7 +411,7 @@ struct samsung_div_clock exynos4_div_clks[] __initdata = {
DIV(none, "div_fimd0", "mout_fimd0", DIV_LCD0, 0, 4),
DIV(none, "div_mipi0", "mout_mipi0", DIV_LCD0, 16, 4),
DIV(none, "div_audio0", "mout_audio0", DIV_MAUDIO, 0, 4),
- DIV(none, "div_pcm0", "sclk_audio0", DIV_MAUDIO, 4, 8),
+ DIV(sclk_pcm0, "sclk_pcm0", "sclk_audio0", DIV_MAUDIO, 4, 8),
DIV(none, "div_mmc0", "mout_mmc0", DIV_FSYS1, 0, 4),
DIV(none, "div_mmc1", "mout_mmc1", DIV_FSYS1, 16, 4),
DIV(none, "div_mmc2", "mout_mmc2", DIV_FSYS2, 0, 4),