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author | Pankaj Dubey <pankaj.dubey@samsung.com> | 2014-03-12 15:56:45 +0100 |
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committer | Tomasz Figa <t.figa@samsung.com> | 2014-05-14 19:16:54 +0200 |
commit | 8432984732b59b333706fceb4cfb5123140be827 (patch) | |
tree | 35e490c270a68d9bbce7ceadcfaf0de03b31f572 /drivers/clk/samsung/clk-pll.h | |
parent | clk/samsung: add support for multiple clock providers (diff) | |
download | linux-8432984732b59b333706fceb4cfb5123140be827.tar.xz linux-8432984732b59b333706fceb4cfb5123140be827.zip |
clk/samsung: add support for pll2550xx
exynos5260 use pll2550xx and it has different bit fields
for P,M,S values as compared to pll2550. Support for
pll2550xx is added here.
Signed-off-by: Pankaj Dubey <pankaj.dubey@samsung.com>
Signed-off-by: Rahul Sharma <rahul.sharma@samsung.com>
Signed-off-by: Arun Kumar K <arun.kk@samsung.com>
Signed-off-by: Tomasz Figa <t.figa@samsung.com>
Diffstat (limited to 'drivers/clk/samsung/clk-pll.h')
-rw-r--r-- | drivers/clk/samsung/clk-pll.h | 1 |
1 files changed, 1 insertions, 0 deletions
diff --git a/drivers/clk/samsung/clk-pll.h b/drivers/clk/samsung/clk-pll.h index 6428bcc6df6f..ec4bc1d45e31 100644 --- a/drivers/clk/samsung/clk-pll.h +++ b/drivers/clk/samsung/clk-pll.h @@ -31,6 +31,7 @@ enum samsung_pll_type { pll_s3c2410_mpll, pll_s3c2410_upll, pll_s3c2440_mpll, + pll_2550xx, }; #define PLL_35XX_RATE(_rate, _m, _p, _s) \ |