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authorSylwester Nawrocki <s.nawrocki@samsung.com>2018-03-14 12:32:26 +0100
committerSylwester Nawrocki <s.nawrocki@samsung.com>2018-03-15 19:27:29 +0100
commit182c084da5d1e4d7c02d913de154cf5167521580 (patch)
treef147e4dc2fd26ea57f437e991a39300e2a8460c0 /drivers/clk/samsung
parentclk: samsung: exynos5250: Add missing clocks for FIMC LITE SYSMMU devices (diff)
downloadlinux-182c084da5d1e4d7c02d913de154cf5167521580.tar.xz
linux-182c084da5d1e4d7c02d913de154cf5167521580.zip
clk: samsung: Add fout=196608001 Hz EPLL rate entry for exynos4412
This additional frequency is required for HDMI audio support on Odroid U3 board. Signed-off-by: Sylwester Nawrocki <s.nawrocki@samsung.com>
Diffstat (limited to 'drivers/clk/samsung')
-rw-r--r--drivers/clk/samsung/clk-exynos4.c1
1 files changed, 1 insertions, 0 deletions
diff --git a/drivers/clk/samsung/clk-exynos4.c b/drivers/clk/samsung/clk-exynos4.c
index edf125525a36..0421960eb963 100644
--- a/drivers/clk/samsung/clk-exynos4.c
+++ b/drivers/clk/samsung/clk-exynos4.c
@@ -1319,6 +1319,7 @@ static const struct samsung_pll_rate_table exynos4x12_apll_rates[] __initconst =
};
static const struct samsung_pll_rate_table exynos4x12_epll_rates[] __initconst = {
+ PLL_36XX_RATE(24 * MHZ, 196608001, 197, 3, 3, -25690),
PLL_36XX_RATE(24 * MHZ, 192000000, 48, 3, 1, 0),
PLL_36XX_RATE(24 * MHZ, 180633605, 45, 3, 1, 10381),
PLL_36XX_RATE(24 * MHZ, 180000000, 45, 3, 1, 0),