diff options
| author | Sylwester Nawrocki <s.nawrocki@samsung.com> | 2018-03-12 11:23:27 +0100 |
|---|---|---|
| committer | Sylwester Nawrocki <s.nawrocki@samsung.com> | 2018-03-12 11:23:27 +0100 |
| commit | 948e068454568789792f9f10c3242c2bfb8ddbdc (patch) | |
| tree | 14e166eaeba6de66016f2ad7ac2a5a27780a71c9 /drivers/clk/samsung | |
| parent | clk: samsung: exynos5420: Add CLK_SET_RATE_PARENT flag to mout_mau_epll_clk (diff) | |
| download | linux-948e068454568789792f9f10c3242c2bfb8ddbdc.tar.xz linux-948e068454568789792f9f10c3242c2bfb8ddbdc.zip | |
clk: samsung: exynos5420: Add more entries to EPLL rate table
Adding these EPLL output frequency entries allows to support all required
audio sample rates on the CODEC and the HDMI interface on Peach-Pit
Chromebook.
Signed-off-by: Sylwester Nawrocki <s.nawrocki@samsung.com>
Acked-by: Chanwoo Choi <cw00.choi@samsung.com>
Signed-off-by: Sylwester Nawrocki <s.nawrocki@samsung.com>
Diffstat (limited to 'drivers/clk/samsung')
| -rw-r--r-- | drivers/clk/samsung/clk-exynos5420.c | 3 |
1 files changed, 3 insertions, 0 deletions
diff --git a/drivers/clk/samsung/clk-exynos5420.c b/drivers/clk/samsung/clk-exynos5420.c index 1bb6e103509f..95e1bf69449b 100644 --- a/drivers/clk/samsung/clk-exynos5420.c +++ b/drivers/clk/samsung/clk-exynos5420.c @@ -1360,8 +1360,11 @@ static const struct samsung_pll_rate_table exynos5420_epll_24mhz_tbl[] = { PLL_36XX_RATE(24 * MHZ, 180633609U, 301, 5, 3, 3671), PLL_36XX_RATE(24 * MHZ, 131072006U, 131, 3, 3, 4719), PLL_36XX_RATE(24 * MHZ, 100000000U, 200, 3, 4, 0), + PLL_36XX_RATE(24 * MHZ, 73728000U, 98, 2, 4, 19923), + PLL_36XX_RATE(24 * MHZ, 67737602U, 90, 2, 4, 20762), PLL_36XX_RATE(24 * MHZ, 65536003U, 131, 3, 4, 4719), PLL_36XX_RATE(24 * MHZ, 49152000U, 197, 3, 5, -25690), + PLL_36XX_RATE(24 * MHZ, 45158401U, 90, 3, 4, 20762), PLL_36XX_RATE(24 * MHZ, 32768001U, 131, 3, 5, 4719), }; |