diff options
| author | Tomasz Figa <t.figa@samsung.com> | 2013-08-26 19:09:11 +0200 |
|---|---|---|
| committer | Mike Turquette <mturquette@linaro.org> | 2013-09-06 22:34:05 +0200 |
| commit | 22e9e7589e7bc6006af983f73e4a4057dbd9da66 (patch) | |
| tree | 66b4939aa07d1c15f25ca6ded05e4cc27fe81e4c /drivers/clk/samsung | |
| parent | clk: samsung: exynos4: Register PLL rate tables for Exynos4x12 (diff) | |
| download | linux-22e9e7589e7bc6006af983f73e4a4057dbd9da66.tar.xz linux-22e9e7589e7bc6006af983f73e4a4057dbd9da66.zip | |
clk: samsung: exynos5250: Simplify registration of PLL rate tables
Since the _get_rate() helper has been modified to use __clk_lookup()
internally, checking of PLL input rates can be done using it and so the
registration code can be simplified.
Signed-off-by: Tomasz Figa <t.figa@samsung.com>
Signed-off-by: Kyungmin Park <kyungmin.park@samsung.com>
Reviewed-by: Sylwester Nawrocki <s.nawrocki@samsung.com>
Signed-off-by: Mike Turquette <mturquette@linaro.org>
Diffstat (limited to 'drivers/clk/samsung')
| -rw-r--r-- | drivers/clk/samsung/clk-exynos5250.c | 12 |
1 files changed, 2 insertions, 10 deletions
diff --git a/drivers/clk/samsung/clk-exynos5250.c b/drivers/clk/samsung/clk-exynos5250.c index d90e59326252..adf32343c9f9 100644 --- a/drivers/clk/samsung/clk-exynos5250.c +++ b/drivers/clk/samsung/clk-exynos5250.c @@ -543,8 +543,6 @@ static struct of_device_id ext_clk_match[] __initdata = { static void __init exynos5250_clk_init(struct device_node *np) { void __iomem *reg_base; - struct clk *vpllsrc; - unsigned long fin_pll_rate, mout_vpllsrc_rate = 0; if (np) { reg_base = of_iomap(np, 0); @@ -563,16 +561,10 @@ static void __init exynos5250_clk_init(struct device_node *np) samsung_clk_register_mux(exynos5250_pll_pmux_clks, ARRAY_SIZE(exynos5250_pll_pmux_clks)); - fin_pll_rate = _get_rate("fin_pll"); - - if (fin_pll_rate == 24 * MHZ) + if (_get_rate("fin_pll") == 24 * MHZ) exynos5250_plls[epll].rate_table = epll_24mhz_tbl; - vpllsrc = __clk_lookup("mout_vpllsrc"); - if (vpllsrc) - mout_vpllsrc_rate = clk_get_rate(vpllsrc); - - if (mout_vpllsrc_rate == 24 * MHZ) + if (_get_rate("mout_vpllsrc") == 24 * MHZ) exynos5250_plls[vpll].rate_table = vpll_24mhz_tbl; samsung_clk_register_pll(exynos5250_plls, ARRAY_SIZE(exynos5250_plls), |