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| author | Dinh Nguyen <dinguyen@opensource.altera.com> | 2015-07-25 05:30:18 +0200 |
|---|---|---|
| committer | Michael Turquette <mturquette@baylibre.com> | 2015-08-25 01:49:03 +0200 |
| commit | 34d5003bfba44a73fe9fbcf75e1d41d130d59bd1 (patch) | |
| tree | 6cb63c13a13c1f257a6c15991cf00dd009864517 /drivers/clk/sirf/clk-atlas7.c | |
| parent | clk: ux500: delete the non-DT U8500 clock implementation (diff) | |
| download | linux-34d5003bfba44a73fe9fbcf75e1d41d130d59bd1.tar.xz linux-34d5003bfba44a73fe9fbcf75e1d41d130d59bd1.zip | |
clk: socfpga: Add a second parent option for the dbg_base_clk
The debug base clock can be bypassed from the main PLL to the OSC1 clock.
The bypass register is the staysoc1(0x10) register that is in the clock
manager.
This patch adds the option to get the correct parent for the debug base
clock.
Signed-off-by: Dinh Nguyen <dinguyen@opensource.altera.com>
Signed-off-by: Stephen Boyd <sboyd@codeaurora.org>
Diffstat (limited to 'drivers/clk/sirf/clk-atlas7.c')
0 files changed, 0 insertions, 0 deletions