diff options
| author | Dinh Nguyen <dinguyen@kernel.org> | 2020-06-16 22:24:17 +0200 |
|---|---|---|
| committer | Stephen Boyd <sboyd@kernel.org> | 2020-06-20 04:27:33 +0200 |
| commit | 44a7f3e8222a7345b72a83a26d6d599bba815cf9 (patch) | |
| tree | a822467e1b7700ac37a020455c0cadad0f93aac1 /drivers/clk/socfpga | |
| parent | clk: socfpga: agilex: add nand_x_clk and nand_ecc_clk (diff) | |
| download | linux-44a7f3e8222a7345b72a83a26d6d599bba815cf9.tar.xz linux-44a7f3e8222a7345b72a83a26d6d599bba815cf9.zip | |
clk: socfpga: agilex: mpu_l2ram_clk should be mpu_ccu_clk
Preliminary documentation documented the mpu_l2ram_clk, but since then,
the mpu_l2ram_clk is no longer documented. It's now referred to as
mpu_ccu_clk.
Signed-off-by: Dinh Nguyen <dinguyen@kernel.org>
Link: https://lore.kernel.org/r/20200616202417.14376-3-dinguyen@kernel.org
Signed-off-by: Stephen Boyd <sboyd@kernel.org>
Diffstat (limited to 'drivers/clk/socfpga')
| -rw-r--r-- | drivers/clk/socfpga/clk-agilex.c | 2 |
1 files changed, 1 insertions, 1 deletions
diff --git a/drivers/clk/socfpga/clk-agilex.c b/drivers/clk/socfpga/clk-agilex.c index 1b2e0ad01b24..8fb12cbe0208 100644 --- a/drivers/clk/socfpga/clk-agilex.c +++ b/drivers/clk/socfpga/clk-agilex.c @@ -252,7 +252,7 @@ static const struct stratix10_gate_clock agilex_gate_clks[] = { 0, 0, 0, 0, 0x30, 0, 0}, { AGILEX_MPU_PERIPH_CLK, "mpu_periph_clk", "mpu_clk", NULL, 1, 0, 0x24, 0, 0, 0, 0, 0, 0, 4}, - { AGILEX_MPU_L2RAM_CLK, "mpu_l2ram_clk", "mpu_clk", NULL, 1, 0, 0x24, + { AGILEX_MPU_CCU_CLK, "mpu_ccu_clk", "mpu_clk", NULL, 1, 0, 0x24, 0, 0, 0, 0, 0, 0, 2}, { AGILEX_L4_MAIN_CLK, "l4_main_clk", "noc_clk", NULL, 1, 0, 0x24, 1, 0x44, 0, 2, 0, 0, 0}, |