diff options
| author | Stefan Agner <stefan@agner.ch> | 2016-04-28 23:07:03 +0200 |
|---|---|---|
| committer | Shawn Guo <shawnguo@kernel.org> | 2016-05-03 14:35:38 +0200 |
| commit | 92a847e3609a8d00bcbe8bdfacbcbbca03135410 (patch) | |
| tree | 9c4b5f7bee694e5820cb099b11d82db2022fdf80 /drivers/clk/socfpga | |
| parent | clk: imx: return correct frequency for Ethernet PLL (diff) | |
| download | linux-92a847e3609a8d00bcbe8bdfacbcbbca03135410.tar.xz linux-92a847e3609a8d00bcbe8bdfacbcbbca03135410.zip | |
clk: imx7d: fix ahb clock mux 1
The clock parent of the AHB root clock when using mux option 1
is the SYS PLL 270MHz clock. This is specified in Table 5-11
Clock Root Table of the i.MX 7Dual Applications Processor
Reference Manual.
While it could be a documentation error, the 270MHz parent is
also mentioned in the boot ROM configuration in Table 6-28: The
clock is by default at 135MHz due to a POST_PODF value of 1
(=> divider of 2).
Signed-off-by: Stefan Agner <stefan@agner.ch>
Signed-off-by: Shawn Guo <shawnguo@kernel.org>
Diffstat (limited to 'drivers/clk/socfpga')
0 files changed, 0 insertions, 0 deletions