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authorViresh Kumar <viresh.kumar@st.com>2012-04-11 14:34:23 +0200
committerArnd Bergmann <arnd@arndb.de>2012-05-12 21:19:26 +0200
commit5335a639ecc5646cbe8e99086fb7e743b801ac58 (patch)
tree812d38780a2eecf385e5f42a4ee3808aa3a85da3 /drivers/clk/spear/clk.h
parentSPEAr: clk: Add VCO-PLL Synthesizer clock (diff)
downloadlinux-5335a639ecc5646cbe8e99086fb7e743b801ac58.tar.xz
linux-5335a639ecc5646cbe8e99086fb7e743b801ac58.zip
SPEAr: clk: Add Auxiliary Synthesizer clock
All SPEAr SoC's contain Auxiliary Synthesizers. Their Fout is derived based on values of eq, x and y. Fout from synthesizer can be given from two equations: Fout1 = (Fin * X/Y)/2 EQ1 Fout2 = Fin * X/Y EQ2 This patch adds in support for this type of clock. Signed-off-by: Viresh Kumar <viresh.kumar@st.com> Reviewed-by: Mike Turquette <mturquette@linaro.org>
Diffstat (limited to '')
-rw-r--r--drivers/clk/spear/clk.h43
1 files changed, 43 insertions, 0 deletions
diff --git a/drivers/clk/spear/clk.h b/drivers/clk/spear/clk.h
index 9979b7f7e767..c2290800503a 100644
--- a/drivers/clk/spear/clk.h
+++ b/drivers/clk/spear/clk.h
@@ -16,6 +16,45 @@
#include <linux/spinlock_types.h>
#include <linux/types.h>
+/* Auxiliary Synth clk */
+/* Default masks */
+#define AUX_EQ_SEL_SHIFT 30
+#define AUX_EQ_SEL_MASK 1
+#define AUX_EQ1_SEL 0
+#define AUX_EQ2_SEL 1
+#define AUX_XSCALE_SHIFT 16
+#define AUX_XSCALE_MASK 0xFFF
+#define AUX_YSCALE_SHIFT 0
+#define AUX_YSCALE_MASK 0xFFF
+#define AUX_SYNT_ENB 31
+
+struct aux_clk_masks {
+ u32 eq_sel_mask;
+ u32 eq_sel_shift;
+ u32 eq1_mask;
+ u32 eq2_mask;
+ u32 xscale_sel_mask;
+ u32 xscale_sel_shift;
+ u32 yscale_sel_mask;
+ u32 yscale_sel_shift;
+ u32 enable_bit;
+};
+
+struct aux_rate_tbl {
+ u16 xscale;
+ u16 yscale;
+ u8 eq;
+};
+
+struct clk_aux {
+ struct clk_hw hw;
+ void __iomem *reg;
+ struct aux_clk_masks *masks;
+ struct aux_rate_tbl *rtbl;
+ u8 rtbl_cnt;
+ spinlock_t *lock;
+};
+
/* VCO-PLL clk */
struct pll_rate_tbl {
u8 mode;
@@ -44,6 +83,10 @@ typedef unsigned long (*clk_calc_rate)(struct clk_hw *hw, unsigned long prate,
int index);
/* clk register routines */
+struct clk *clk_register_aux(const char *aux_name, const char *gate_name,
+ const char *parent_name, unsigned long flags, void __iomem *reg,
+ struct aux_clk_masks *masks, struct aux_rate_tbl *rtbl,
+ u8 rtbl_cnt, spinlock_t *lock, struct clk **gate_clk);
struct clk *clk_register_vco_pll(const char *vco_name, const char *pll_name,
const char *vco_gate_name, const char *parent_name,
unsigned long flags, void __iomem *mode_reg, void __iomem