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author | Stephen Boyd <sboyd@kernel.org> | 2024-07-01 22:25:33 +0200 |
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committer | Stephen Boyd <sboyd@kernel.org> | 2024-07-01 22:25:33 +0200 |
commit | af05917c221e97d723017b157e6e2d373f81a47f (patch) | |
tree | f3d7b60bc24154fd40a23ae7142eb6ce2ae9a908 /drivers/clk/starfive | |
parent | Linux 6.10-rc1 (diff) | |
parent | clk: imx: composite-7ulp: Use NULL instead of 0 (diff) | |
download | linux-af05917c221e97d723017b157e6e2d373f81a47f.tar.xz linux-af05917c221e97d723017b157e6e2d373f81a47f.zip |
Merge tag 'clk-imx-6.11' of git://git.kernel.org/pub/scm/linux/kernel/git/abelvesa/linux into clk-imx
Pull i.MX clk driver updates from Abel Vesa:
- Add reset controller support to audiomix block control
- Add CLK_SET_RATE_PARENT flag to all audiomix clocks and to
i.MX7D lcdif_pixel_src clock
- Fix parent clocks for earc_phy and audpll on i.MX8MP
- Fix default parents for enet[12]_ref_sel on i.MX6UL
- Add ops in composite 8M and 93 that allow no-op on disable
- Add check for PCC present bit on composite 7ULP register
- Fix fractional part for fracn-gppll on prepare
- Fix clock tree update for TF-A managed clocks on i.MX8M
- Drop CLK_SET_PARENT_GATE for DRAM mux on i.MX7D
- Add the SAI7 IPG clock for i.MX8MN
- Mark the 'nand_usdhc_bus' clock as non-critical on i.MX8MM
- Add LVDS bypass clocks on i.MX8QXP
- Add muxes for MIPI and PHY ref clocks
- Reorder dc0_bypass0_clk, lcd_pxl and dc1_disp clocks on i.MX8QXP
- Add 1039.5MHz and 800MHz rates to fracn-gppll table
- Add CLK_SET_RATE_PARENT for media_disp pixel clocks on i.MX8QXP
- Add some module descriptions to the i.MX generic and the
i.MXRT1050 driver.
- Fix return value for bypass for composite 7ULP
* tag 'clk-imx-6.11' of git://git.kernel.org/pub/scm/linux/kernel/git/abelvesa/linux: (22 commits)
clk: imx: composite-7ulp: Use NULL instead of 0
clk: imx: add missing MODULE_DESCRIPTION() macros
clk: imx: clk-imx8mp: Allow media_disp pixel clock reconfigure parent rate
clk: imx: fracn-gppll: update rate table
clk: imx: imx8qxp: Parent should be initialized earlier than the clock
clk: imx: imx8qxp: Register dc0_bypass0_clk before disp clk
clk: imx: imx8qxp: Add clock muxes for MIPI and PHY ref clocks
clk: imx: imx8qxp: Add LVDS bypass clocks
clk: imx: imx8mm: Change the 'nand_usdhc_bus' clock to non-critical one
clk: imx: imx8mn: add sai7_ipg_clk clock settings
clk: imx: add CLK_SET_RATE_PARENT for lcdif_pixel_src for i.MX7D
clk: imx: Remove CLK_SET_PARENT_GATE for DRAM mux for i.MX7D
clk: imx: imx8mp: fix clock tree update of TF-A managed clocks
clk: imx: fracn-gppll: fix fractional part of PLL getting lost
clk: imx: composite-7ulp: Check the PCC present bit
clk: imx: composite-93: keep root clock on when mcore enabled
clk: imx: composite-8m: Enable gate clk with mcore_booted
clk: imx: imx6ul: fix default parent for enet*_ref_sel
clk: imx: clk-audiomix: Correct parent clock for earc_phy and audpll
clk: imx: clk-audiomix: Add CLK_SET_RATE_PARENT flags for clocks
...
Diffstat (limited to 'drivers/clk/starfive')
0 files changed, 0 insertions, 0 deletions