diff options
| author | Jernej Skrabec <jernej.skrabec@siol.net> | 2019-02-28 21:03:27 +0100 |
|---|---|---|
| committer | Maxime Ripard <maxime.ripard@bootlin.com> | 2019-03-18 08:07:21 +0100 |
| commit | ab65e04dc101d55f1509059725cf9d331141f6e8 (patch) | |
| tree | fa6aa2d2464fd4eca74fd298fd4a602a1714c6d5 /drivers/clk/sunxi-ng/ccu-sun50i-a64.c | |
| parent | Linux 5.1-rc1 (diff) | |
| download | linux-ab65e04dc101d55f1509059725cf9d331141f6e8.tar.xz linux-ab65e04dc101d55f1509059725cf9d331141f6e8.zip | |
clk: sunxi-ng: Allow DE clock to set parent rate
DE2/DE3 mixers have to run at specific frequency in order to work
optimally. This wasn't actually possible for some SoCs because "de"
clock wasn't allowed to adjust parent rate.
Add CLK_SET_RATE_PARENT flag to all "de" clocks which didn't have it
yet.
Signed-off-by: Jernej Skrabec <jernej.skrabec@siol.net>
Signed-off-by: Maxime Ripard <maxime.ripard@bootlin.com>
Diffstat (limited to 'drivers/clk/sunxi-ng/ccu-sun50i-a64.c')
| -rw-r--r-- | drivers/clk/sunxi-ng/ccu-sun50i-a64.c | 3 |
1 files changed, 2 insertions, 1 deletions
diff --git a/drivers/clk/sunxi-ng/ccu-sun50i-a64.c b/drivers/clk/sunxi-ng/ccu-sun50i-a64.c index 932836d26e2b..be0deee70182 100644 --- a/drivers/clk/sunxi-ng/ccu-sun50i-a64.c +++ b/drivers/clk/sunxi-ng/ccu-sun50i-a64.c @@ -531,7 +531,8 @@ static SUNXI_CCU_GATE(dram_ts_clk, "dram-ts", "dram", static const char * const de_parents[] = { "pll-periph0-2x", "pll-de" }; static SUNXI_CCU_M_WITH_MUX_GATE(de_clk, "de", de_parents, - 0x104, 0, 4, 24, 3, BIT(31), 0); + 0x104, 0, 4, 24, 3, BIT(31), + CLK_SET_RATE_PARENT); static const char * const tcon0_parents[] = { "pll-mipi", "pll-video0-2x" }; static const u8 tcon0_table[] = { 0, 2, }; |