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| author | Priit Laes <plaes@plaes.org> | 2017-03-02 21:55:27 +0100 |
|---|---|---|
| committer | Maxime Ripard <maxime.ripard@free-electrons.com> | 2017-03-06 10:25:56 +0100 |
| commit | b0f0daa8fe9e74b85f6360288d38224ad1c2f2f4 (patch) | |
| tree | 1f0b619bb03802fdfd07dd854b3c11f6973e5b81 /drivers/clk/sunxi-ng/ccu-sun5i.c | |
| parent | clk: sunxi-ng: tighten SoC deps on explicit AllWinner SoCs (diff) | |
| download | linux-b0f0daa8fe9e74b85f6360288d38224ad1c2f2f4.tar.xz linux-b0f0daa8fe9e74b85f6360288d38224ad1c2f2f4.zip | |
clk: sunxi-ng: sun5i: Fix mux width for csi clock
Mux for CSI clock is 3 bits, not 2.
Signed-off-by: Priit Laes <plaes@plaes.org>
Signed-off-by: Maxime Ripard <maxime.ripard@free-electrons.com>
Diffstat (limited to 'drivers/clk/sunxi-ng/ccu-sun5i.c')
| -rw-r--r-- | drivers/clk/sunxi-ng/ccu-sun5i.c | 2 |
1 files changed, 1 insertions, 1 deletions
diff --git a/drivers/clk/sunxi-ng/ccu-sun5i.c b/drivers/clk/sunxi-ng/ccu-sun5i.c index 06edaa523479..5c476f966a72 100644 --- a/drivers/clk/sunxi-ng/ccu-sun5i.c +++ b/drivers/clk/sunxi-ng/ccu-sun5i.c @@ -469,7 +469,7 @@ static const char * const csi_parents[] = { "hosc", "pll-video0", "pll-video1", static const u8 csi_table[] = { 0, 1, 2, 5, 6 }; static SUNXI_CCU_M_WITH_MUX_TABLE_GATE(csi_clk, "csi", csi_parents, csi_table, - 0x134, 0, 5, 24, 2, BIT(31), 0); + 0x134, 0, 5, 24, 3, BIT(31), 0); static SUNXI_CCU_GATE(ve_clk, "ve", "pll-ve", 0x13c, BIT(31), CLK_SET_RATE_PARENT); |