diff options
author | Chen-Yu Tsai <wens@csie.org> | 2017-05-19 09:06:08 +0200 |
---|---|---|
committer | Maxime Ripard <maxime.ripard@free-electrons.com> | 2017-06-07 15:32:15 +0200 |
commit | 13e0dde8b2ed043aa3e65437342d501715d975c1 (patch) | |
tree | ebc8e171a82bb4743fbcc27de067fcf79a261046 /drivers/clk/sunxi-ng/ccu-sun6i-a31.c | |
parent | dt-bindings: clock: sunxi-ccu: Add compatible string for A83T CCU (diff) | |
download | linux-13e0dde8b2ed043aa3e65437342d501715d975c1.tar.xz linux-13e0dde8b2ed043aa3e65437342d501715d975c1.zip |
clk: sunxi-ng: Support multiple variable pre-dividers
On the A83T, the AHB1 clock has a shared pre-divider on the two
PLL-PERIPH clock parents. To support such instances of shared
pre-dividers, this patch extends the mux clock type to support
multiple variable pre-dividers.
As the pre-dividers are only used to calculate the rate, but
do not participate in the factorization process, this is fairly
straightforward.
Signed-off-by: Chen-Yu Tsai <wens@csie.org>
Signed-off-by: Maxime Ripard <maxime.ripard@free-electrons.com>
Diffstat (limited to 'drivers/clk/sunxi-ng/ccu-sun6i-a31.c')
-rw-r--r-- | drivers/clk/sunxi-ng/ccu-sun6i-a31.c | 10 |
1 files changed, 5 insertions, 5 deletions
diff --git a/drivers/clk/sunxi-ng/ccu-sun6i-a31.c b/drivers/clk/sunxi-ng/ccu-sun6i-a31.c index df97e25aec76..4d6078fca9ac 100644 --- a/drivers/clk/sunxi-ng/ccu-sun6i-a31.c +++ b/drivers/clk/sunxi-ng/ccu-sun6i-a31.c @@ -195,6 +195,9 @@ static SUNXI_CCU_DIV_TABLE(axi_clk, "axi", "cpu", static const char * const ahb1_parents[] = { "osc32k", "osc24M", "axi", "pll-periph" }; +static const struct ccu_mux_var_prediv ahb1_predivs[] = { + { .index = 3, .shift = 6, .width = 2 }, +}; static struct ccu_div ahb1_clk = { .div = _SUNXI_CCU_DIV_FLAGS(4, 2, CLK_DIVIDER_POWER_OF_TWO), @@ -203,11 +206,8 @@ static struct ccu_div ahb1_clk = { .shift = 12, .width = 2, - .variable_prediv = { - .index = 3, - .shift = 6, - .width = 2, - }, + .var_predivs = ahb1_predivs, + .n_var_predivs = ARRAY_SIZE(ahb1_predivs), }, .common = { |