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| author | Jernej Skrabec <jernej.skrabec@siol.net> | 2018-08-09 18:52:14 +0200 |
|---|---|---|
| committer | Maxime Ripard <maxime.ripard@bootlin.com> | 2018-08-27 09:18:08 +0200 |
| commit | 02d7901695afd1dcbec7182d878927893c07174e (patch) | |
| tree | b7f59ec45ebd891c225d48c85f3b6cfe4f0c45c6 /drivers/clk/sunxi-ng/ccu-sun8i-r40.c | |
| parent | clk: sunxi-ng: Add maximum rate constraint to NM PLLs (diff) | |
| download | linux-02d7901695afd1dcbec7182d878927893c07174e.tar.xz linux-02d7901695afd1dcbec7182d878927893c07174e.zip | |
clk: sunxi-ng: h3/h5: Add max. rate constraint to pll-video
As it turns out, pll-video can be set to higher rate that it is really
supported by HW.
For example, one monitor requested 185.58 MHz pixel clock. Clock
framework calculated that minimum rate error would be when pll-video
is set to 2040 MHz. This is clearly out of specs.
Both H3 and H5 user manuals specify 600 MHz as maximum supported rate.
However, BSP clock drivers allow up to 912 MHz and 1008 MHz
respectively. Here 912 MHz is chosen because user manuals were already
proven wrong once for lower limits.
Signed-off-by: Jernej Skrabec <jernej.skrabec@siol.net>
Signed-off-by: Maxime Ripard <maxime.ripard@bootlin.com>
Diffstat (limited to 'drivers/clk/sunxi-ng/ccu-sun8i-r40.c')
0 files changed, 0 insertions, 0 deletions