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authorIcenowy Zheng <icenowy@aosc.io>2019-03-14 12:21:08 +0100
committerMaxime Ripard <maxime.ripard@bootlin.com>2019-03-18 08:07:21 +0100
commit6630aad719bc0a46dcc4a6732ab783c4c9b80f88 (patch)
tree5dc7bad92780d824727d649d60222487c28b9096 /drivers/clk/sunxi-ng/ccu_common.c
parentclk: sunxi-ng: Allow DE clock to set parent rate (diff)
downloadlinux-6630aad719bc0a46dcc4a6732ab783c4c9b80f88.tar.xz
linux-6630aad719bc0a46dcc4a6732ab783c4c9b80f88.zip
clk: sunxi-ng: f1c100s: fix USB PHY gate bit offset
The bit offset of the USB PHY clock gate on F1C100s should be 1, not 8. Fix this problem. Fixes: 0380126eb9af ("clk: sunxi-ng: add support for suniv F1C100s SoC") Signed-off-by: Icenowy Zheng <icenowy@aosc.io> Signed-off-by: Maxime Ripard <maxime.ripard@bootlin.com>
Diffstat (limited to 'drivers/clk/sunxi-ng/ccu_common.c')
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