diff options
| author | Jagan Teki <jagan@amarulasolutions.com> | 2018-11-13 12:16:08 +0100 |
|---|---|---|
| committer | Maxime Ripard <maxime.ripard@bootlin.com> | 2018-11-13 14:07:58 +0100 |
| commit | ee678706e46d0d185c27cc214ad97828e0643159 (patch) | |
| tree | c03a4ad3e86c59a832ba85c2ed213dd3f87e7375 /drivers/clk/sunxi-ng | |
| parent | clk: sunxi-ng: Enable DE2_CCU for SUN8I and SUN50I (diff) | |
| download | linux-ee678706e46d0d185c27cc214ad97828e0643159.tar.xz linux-ee678706e46d0d185c27cc214ad97828e0643159.zip | |
clk: sunxi-ng: a64: Fix gate bit of DSI DPHY
DSI DPHY gate bit on MIPI DSI clock register is bit 15
not bit 30.
Signed-off-by: Jagan Teki <jagan@amarulasolutions.com>
Acked-by: Stephen Boyd <sboyd@kernel.org>
Signed-off-by: Maxime Ripard <maxime.ripard@bootlin.com>
Diffstat (limited to 'drivers/clk/sunxi-ng')
| -rw-r--r-- | drivers/clk/sunxi-ng/ccu-sun50i-a64.c | 2 |
1 files changed, 1 insertions, 1 deletions
diff --git a/drivers/clk/sunxi-ng/ccu-sun50i-a64.c b/drivers/clk/sunxi-ng/ccu-sun50i-a64.c index 884d8f7863c4..1f45b20ad752 100644 --- a/drivers/clk/sunxi-ng/ccu-sun50i-a64.c +++ b/drivers/clk/sunxi-ng/ccu-sun50i-a64.c @@ -586,7 +586,7 @@ static const char * const dsi_dphy_parents[] = { "pll-video0", "pll-periph0" }; static const u8 dsi_dphy_table[] = { 0, 2, }; static SUNXI_CCU_M_WITH_MUX_TABLE_GATE(dsi_dphy_clk, "dsi-dphy", dsi_dphy_parents, dsi_dphy_table, - 0x168, 0, 4, 8, 2, BIT(31), CLK_SET_RATE_PARENT); + 0x168, 0, 4, 8, 2, BIT(15), CLK_SET_RATE_PARENT); static SUNXI_CCU_M_WITH_GATE(gpu_clk, "gpu", "pll-gpu", 0x1a0, 0, 3, BIT(31), CLK_SET_RATE_PARENT); |