diff options
| author | Peter De Schrijver <pdeschrijver@nvidia.com> | 2013-11-25 13:44:13 +0100 |
|---|---|---|
| committer | Peter De Schrijver <pdeschrijver@nvidia.com> | 2013-11-26 17:46:21 +0100 |
| commit | 8e9cc80aa348938078c3c1a7ab55efb3c40990e3 (patch) | |
| tree | 28f27ff2c2a39de09c0ec3a0f100b5c5243f0646 /drivers/clk/tegra/clk-pll.c | |
| parent | clk: tegra: move some PLLC and PLLXC init to clk-pll.c (diff) | |
| download | linux-8e9cc80aa348938078c3c1a7ab55efb3c40990e3.tar.xz linux-8e9cc80aa348938078c3c1a7ab55efb3c40990e3.zip | |
clk: tegra: use pll_ref as the pll_e parent
Use pll_ref instead of pll_re_vco as the pll_e parent on Tegra114. Also
add a 12Mhz pll_ref table entry for pll_e for Tegra114. This prevents
the system from crashing at bootup because of an unsupported pll_re_vco
rate.
Signed-off-by: Peter De Schrijver <pdeschrijver@nvidia.com>
Diffstat (limited to 'drivers/clk/tegra/clk-pll.c')
| -rw-r--r-- | drivers/clk/tegra/clk-pll.c | 8 |
1 files changed, 5 insertions, 3 deletions
diff --git a/drivers/clk/tegra/clk-pll.c b/drivers/clk/tegra/clk-pll.c index 8f51147185db..48f6bffc1cee 100644 --- a/drivers/clk/tegra/clk-pll.c +++ b/drivers/clk/tegra/clk-pll.c @@ -1704,11 +1704,13 @@ struct clk *tegra_clk_register_plle_tegra114(const char *name, val_aux = pll_readl(pll_params->aux_reg, pll); if (val & PLL_BASE_ENABLE) { - if (!(val_aux & PLLE_AUX_PLLRE_SEL)) + if ((val_aux & PLLE_AUX_PLLRE_SEL) || + (val_aux & PLLE_AUX_PLLP_SEL)) WARN(1, "pll_e enabled with unsupported parent %s\n", - (val & PLLE_AUX_PLLP_SEL) ? "pllp_out0" : "pll_ref"); + (val_aux & PLLE_AUX_PLLP_SEL) ? "pllp_out0" : + "pll_re_vco"); } else { - val_aux |= PLLE_AUX_PLLRE_SEL; + val_aux &= ~(PLLE_AUX_PLLRE_SEL | PLLE_AUX_PLLP_SEL); pll_writel(val, pll_params->aux_reg, pll); } |