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| author | Mark Zhang <markz@nvidia.com> | 2013-08-07 13:25:07 +0200 |
|---|---|---|
| committer | Peter De Schrijver <pdeschrijver@nvidia.com> | 2013-11-25 15:11:43 +0100 |
| commit | d17cb95fa0b8676a38c0d07e2da26885d4ff8187 (patch) | |
| tree | 5327f640c8a0b7a47e2e8be2c0092fe7178c28d4 /drivers/clk/tegra/clk-pll.c | |
| parent | clk: tegra: Correct sbc mux width & parent (diff) | |
| download | linux-d17cb95fa0b8676a38c0d07e2da26885d4ff8187.tar.xz linux-d17cb95fa0b8676a38c0d07e2da26885d4ff8187.zip | |
clk: tegra: Fix vde/2d/3d clock src offset
In Tegra114, vde/gr_2d/gr_3d have 3 bits for clock source selection.
So change the clock init macro for these clocks from
"TEGRA_INIT_DATA_INT" to "TEGRA_INIT_DATA_INT8".
Besides, no one uses "TEGRA_INIT_DATA_INT" after this change, so
remove this macro.
Signed-off-by: Mark Zhang <markz@nvidia.com>
Acked-by: Stephen Warren <swarren@nvidia.com>
Acked-By: Peter De Schrijver <pdeschrijver@nvidia.com>
Diffstat (limited to 'drivers/clk/tegra/clk-pll.c')
0 files changed, 0 insertions, 0 deletions