diff options
| author | JC Kuo <jckuo@nvidia.com> | 2021-01-20 08:34:02 +0100 |
|---|---|---|
| committer | Thierry Reding <treding@nvidia.com> | 2021-03-24 14:02:14 +0100 |
| commit | 0c7ea2b1c850756140fef03bed0fbaf0957f120a (patch) | |
| tree | a32863a42509224fa63a063185144946f80bb4b9 /drivers/clk/tegra/clk-pll.c | |
| parent | clk: tegra: Add PLLE HW power sequencer control (diff) | |
| download | linux-0c7ea2b1c850756140fef03bed0fbaf0957f120a.tar.xz linux-0c7ea2b1c850756140fef03bed0fbaf0957f120a.zip | |
clk: tegra: Don't enable PLLE HW sequencer at init
PLLE hardware power sequencer references PEX/SATA UPHY PLL hardware
power sequencers' output to enable/disable PLLE. PLLE hardware power
sequencer has to be enabled only after PEX/SATA UPHY PLL's sequencers
are enabled.
Signed-off-by: JC Kuo <jckuo@nvidia.com>
Acked-by: Thierry Reding <treding@nvidia.com>
Acked-by: Stephen Boyd <sboyd@kernel.org>
Signed-off-by: Thierry Reding <treding@nvidia.com>
Diffstat (limited to 'drivers/clk/tegra/clk-pll.c')
| -rw-r--r-- | drivers/clk/tegra/clk-pll.c | 12 |
1 files changed, 0 insertions, 12 deletions
diff --git a/drivers/clk/tegra/clk-pll.c b/drivers/clk/tegra/clk-pll.c index c5cc0a2dac6f..0193cebe8c5a 100644 --- a/drivers/clk/tegra/clk-pll.c +++ b/drivers/clk/tegra/clk-pll.c @@ -2515,18 +2515,6 @@ static int clk_plle_tegra210_enable(struct clk_hw *hw) pll_writel(val, PLLE_SS_CTRL, pll); udelay(1); - val = pll_readl_misc(pll); - val &= ~PLLE_MISC_IDDQ_SW_CTRL; - pll_writel_misc(val, pll); - - val = pll_readl(pll->params->aux_reg, pll); - val |= (PLLE_AUX_USE_LOCKDET | PLLE_AUX_SS_SEQ_INCLUDE); - val &= ~(PLLE_AUX_ENABLE_SWCTL | PLLE_AUX_SS_SWCTL); - pll_writel(val, pll->params->aux_reg, pll); - udelay(1); - val |= PLLE_AUX_SEQ_ENABLE; - pll_writel(val, pll->params->aux_reg, pll); - out: if (pll->lock) spin_unlock_irqrestore(pll->lock, flags); |