diff options
author | Rhyland Klein <rklein@nvidia.com> | 2015-06-18 23:28:36 +0200 |
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committer | Thierry Reding <treding@nvidia.com> | 2015-12-17 13:37:56 +0100 |
commit | 6b301a059eb2ebed1b12a900e3b21a38e48dd410 (patch) | |
tree | 52cb25fb0297134f7f137b41bf77941dd7f4f585 /drivers/clk/tegra/clk-pll.c | |
parent | clk: tegra: Add Super Gen5 Logic (diff) | |
download | linux-6b301a059eb2ebed1b12a900e3b21a38e48dd410.tar.xz linux-6b301a059eb2ebed1b12a900e3b21a38e48dd410.zip |
clk: tegra: Add support for Tegra210 clocks
Implement clock support for Tegra210.
Signed-off-by: Rhyland Klein <rklein@nvidia.com>
Signed-off-by: Thierry Reding <treding@nvidia.com>
Diffstat (limited to 'drivers/clk/tegra/clk-pll.c')
-rw-r--r-- | drivers/clk/tegra/clk-pll.c | 5 |
1 files changed, 5 insertions, 0 deletions
diff --git a/drivers/clk/tegra/clk-pll.c b/drivers/clk/tegra/clk-pll.c index 7ef08861c35d..d00e3289eb79 100644 --- a/drivers/clk/tegra/clk-pll.c +++ b/drivers/clk/tegra/clk-pll.c @@ -414,6 +414,11 @@ static int _p_div_to_hw(struct clk_hw *hw, u8 p_div) return -EINVAL; } +int tegra_pll_p_div_to_hw(struct tegra_clk_pll *pll, u8 p_div) +{ + return _p_div_to_hw(&pll->hw, p_div); +} + static int _hw_to_p_div(struct clk_hw *hw, u8 p_div_hw) { struct tegra_clk_pll *pll = to_clk_pll(hw); |