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authorDmitry Osipenko <digetx@gmail.com>2017-10-04 01:02:38 +0200
committerThierry Reding <treding@nvidia.com>2017-11-01 15:00:04 +0100
commit899f8095e66c562888ff617686e46019b758611b (patch)
treec421ea3751b4bfcaff70a96f7d733b6e890fc672 /drivers/clk/tegra/clk-tegra-periph.c
parentclk: tegra: Mark APB clock as critical (diff)
downloadlinux-899f8095e66c562888ff617686e46019b758611b.tar.xz
linux-899f8095e66c562888ff617686e46019b758611b.zip
clk: tegra: Add AHB DMA clock entry
AHB DMA engine presents on Tegra20/30. Add missing clock entries, so that driver for the AHB DMA controller could be implemented. Signed-off-by: Dmitry Osipenko <digetx@gmail.com> Signed-off-by: Thierry Reding <treding@nvidia.com>
Diffstat (limited to 'drivers/clk/tegra/clk-tegra-periph.c')
-rw-r--r--drivers/clk/tegra/clk-tegra-periph.c1
1 files changed, 1 insertions, 0 deletions
diff --git a/drivers/clk/tegra/clk-tegra-periph.c b/drivers/clk/tegra/clk-tegra-periph.c
index c7694205573f..f5232d6d203d 100644
--- a/drivers/clk/tegra/clk-tegra-periph.c
+++ b/drivers/clk/tegra/clk-tegra-periph.c
@@ -807,6 +807,7 @@ static struct tegra_periph_init_data gate_clks[] = {
GATE("timer", "clk_m", 5, 0, tegra_clk_timer, CLK_IS_CRITICAL),
GATE("isp", "clk_m", 23, 0, tegra_clk_isp, 0),
GATE("vcp", "clk_m", 29, 0, tegra_clk_vcp, 0),
+ GATE("ahbdma", "hclk", 33, 0, tegra_clk_ahbdma, 0),
GATE("apbdma", "clk_m", 34, 0, tegra_clk_apbdma, 0),
GATE("kbc", "clk_32k", 36, TEGRA_PERIPH_ON_APB | TEGRA_PERIPH_NO_RESET, tegra_clk_kbc, 0),
GATE("fuse", "clk_m", 39, TEGRA_PERIPH_ON_APB, tegra_clk_fuse, 0),