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authorMark Zhang <markz@nvidia.com>2014-12-09 07:59:59 +0100
committerPeter De Schrijver <pdeschrijver@nvidia.com>2015-02-02 15:22:34 +0100
commitb270491eb9a033a1ab6c66e778c9dd3e3a4f7639 (patch)
tree4b0c4d9b987aa11332a5a2f774c0beb7c78f0a6e /drivers/clk/tegra/clk-tegra-periph.c
parentclk: tegra: Add support for the Tegra132 CAR IP block (diff)
downloadlinux-b270491eb9a033a1ab6c66e778c9dd3e3a4f7639.tar.xz
linux-b270491eb9a033a1ab6c66e778c9dd3e3a4f7639.zip
clk: tegra: Define PLLD_DSI and remove dsia(b)_mux
PLLD is the only parent for DSIA & DSIB on Tegra124 and Tegra132. Besides, BIT 30 in PLLD_MISC register controls the output of DSI clock. So this patch removes "dsia_mux" & "dsib_mux", and create a new clock "plld_dsi" to represent the DSI clock enable control. Signed-off-by: Peter De Schrijver <pdeschrijver@nvidia.com> Signed-off-by: Mark Zhang <markz@nvidia.com>
Diffstat (limited to 'drivers/clk/tegra/clk-tegra-periph.c')
-rw-r--r--drivers/clk/tegra/clk-tegra-periph.c2
1 files changed, 0 insertions, 2 deletions
diff --git a/drivers/clk/tegra/clk-tegra-periph.c b/drivers/clk/tegra/clk-tegra-periph.c
index fa20002fb422..cef0727b9eec 100644
--- a/drivers/clk/tegra/clk-tegra-periph.c
+++ b/drivers/clk/tegra/clk-tegra-periph.c
@@ -537,8 +537,6 @@ static struct tegra_periph_init_data gate_clks[] = {
GATE("xusb_host", "xusb_host_src", 89, 0, tegra_clk_xusb_host, 0),
GATE("xusb_ss", "xusb_ss_src", 156, 0, tegra_clk_xusb_ss, 0),
GATE("xusb_dev", "xusb_dev_src", 95, 0, tegra_clk_xusb_dev, 0),
- GATE("dsia", "dsia_mux", 48, 0, tegra_clk_dsia, 0),
- GATE("dsib", "dsib_mux", 82, 0, tegra_clk_dsib, 0),
GATE("emc", "emc_mux", 57, 0, tegra_clk_emc, CLK_IGNORE_UNUSED),
GATE("sata_cold", "clk_m", 129, TEGRA_PERIPH_ON_APB, tegra_clk_sata_cold, 0),
GATE("ispb", "clk_m", 3, 0, tegra_clk_ispb, 0),