diff options
| author | Dmitry Osipenko <digetx@gmail.com> | 2018-01-10 14:59:42 +0100 |
|---|---|---|
| committer | Thierry Reding <treding@nvidia.com> | 2018-03-12 13:58:58 +0100 |
| commit | 2dcabf053c6ecde46f7aa3612c5a57fb8bd185c4 (patch) | |
| tree | 7fdbda65b1f0049027e070ade27d3fe415db6d6c /drivers/clk/tegra/clk-tegra-super-gen4.c | |
| parent | clk: tegra: MBIST work around for Tegra210 (diff) | |
| download | linux-2dcabf053c6ecde46f7aa3612c5a57fb8bd185c4.tar.xz linux-2dcabf053c6ecde46f7aa3612c5a57fb8bd185c4.zip | |
clk: tegra: Mark HCLK, SCLK and EMC as critical
Machine dies if HCLK, SCLK or EMC is disabled. Hence mark these clocks
as critical.
Signed-off-by: Dmitry Osipenko <digetx@gmail.com>
Acked-by: Peter De Schrijver <pdeschrijver@nvidia.com>
Cc: <stable@vger.kernel.org> # v4.16
Signed-off-by: Thierry Reding <treding@nvidia.com>
Diffstat (limited to 'drivers/clk/tegra/clk-tegra-super-gen4.c')
| -rw-r--r-- | drivers/clk/tegra/clk-tegra-super-gen4.c | 8 |
1 files changed, 5 insertions, 3 deletions
diff --git a/drivers/clk/tegra/clk-tegra-super-gen4.c b/drivers/clk/tegra/clk-tegra-super-gen4.c index 10047107c1dc..89d6b47a27a8 100644 --- a/drivers/clk/tegra/clk-tegra-super-gen4.c +++ b/drivers/clk/tegra/clk-tegra-super-gen4.c @@ -125,7 +125,8 @@ static void __init tegra_sclk_init(void __iomem *clk_base, /* SCLK */ dt_clk = tegra_lookup_dt_id(tegra_clk_sclk, tegra_clks); if (dt_clk) { - clk = clk_register_divider(NULL, "sclk", "sclk_mux", 0, + clk = clk_register_divider(NULL, "sclk", "sclk_mux", + CLK_IS_CRITICAL, clk_base + SCLK_DIVIDER, 0, 8, 0, &sysrate_lock); *dt_clk = clk; @@ -137,7 +138,8 @@ static void __init tegra_sclk_init(void __iomem *clk_base, clk = tegra_clk_register_super_mux("sclk", gen_info->sclk_parents, gen_info->num_sclk_parents, - CLK_SET_RATE_PARENT, + CLK_SET_RATE_PARENT | + CLK_IS_CRITICAL, clk_base + SCLK_BURST_POLICY, 0, 4, 0, 0, NULL); *dt_clk = clk; @@ -151,7 +153,7 @@ static void __init tegra_sclk_init(void __iomem *clk_base, clk_base + SYSTEM_CLK_RATE, 4, 2, 0, &sysrate_lock); clk = clk_register_gate(NULL, "hclk", "hclk_div", - CLK_SET_RATE_PARENT | CLK_IGNORE_UNUSED, + CLK_SET_RATE_PARENT | CLK_IS_CRITICAL, clk_base + SYSTEM_CLK_RATE, 7, CLK_GATE_SET_TO_DISABLE, &sysrate_lock); *dt_clk = clk; |