diff options
| author | Peter De Schrijver <pdeschrijver@nvidia.com> | 2013-02-07 17:37:35 +0100 |
|---|---|---|
| committer | Stephen Warren <swarren@nvidia.com> | 2013-02-12 18:29:13 +0100 |
| commit | d076a206b2dfa8ef7a735289fe1221e77d1fa83f (patch) | |
| tree | d579f122ee8adadadf09dec5e01984e67837367a /drivers/clk/tegra/clk-tegra20.c | |
| parent | clk: tegra: Implement locking for super clock (diff) | |
| download | linux-d076a206b2dfa8ef7a735289fe1221e77d1fa83f.tar.xz linux-d076a206b2dfa8ef7a735289fe1221e77d1fa83f.zip | |
clk: tegra: Add missing spinlock for hclk and pclk
The hclk and pclk clocks are controlled by the same register. Hence a lock is
required to avoid corruption.
Signed-off-by: Peter De Schrijver <pdeschrijver@nvidia.com>
Acked-by: Mike Turquette <mturquette@linaro.org>
Reviewed-by: Prashant Gaikwad <pgaikwad@nvidia.com>
Signed-off-by: Stephen Warren <swarren@nvidia.com>
Diffstat (limited to 'drivers/clk/tegra/clk-tegra20.c')
| -rw-r--r-- | drivers/clk/tegra/clk-tegra20.c | 11 |
1 files changed, 7 insertions, 4 deletions
diff --git a/drivers/clk/tegra/clk-tegra20.c b/drivers/clk/tegra/clk-tegra20.c index 5d41569883a7..4612b2e4a5a9 100644 --- a/drivers/clk/tegra/clk-tegra20.c +++ b/drivers/clk/tegra/clk-tegra20.c @@ -194,6 +194,7 @@ static void __iomem *clk_base; static void __iomem *pmc_base; static DEFINE_SPINLOCK(pll_div_lock); +static DEFINE_SPINLOCK(sysrate_lock); #define TEGRA_INIT_DATA_MUX(_name, _con_id, _dev_id, _parents, _offset, \ _clk_num, _regs, _gate_flags, _clk_id) \ @@ -768,19 +769,21 @@ static void tegra20_super_clk_init(void) /* HCLK */ clk = clk_register_divider(NULL, "hclk_div", "sclk", 0, - clk_base + CLK_SYSTEM_RATE, 4, 2, 0, NULL); + clk_base + CLK_SYSTEM_RATE, 4, 2, 0, + &sysrate_lock); clk = clk_register_gate(NULL, "hclk", "hclk_div", CLK_SET_RATE_PARENT, clk_base + CLK_SYSTEM_RATE, 7, - CLK_GATE_SET_TO_DISABLE, NULL); + CLK_GATE_SET_TO_DISABLE, &sysrate_lock); clk_register_clkdev(clk, "hclk", NULL); clks[hclk] = clk; /* PCLK */ clk = clk_register_divider(NULL, "pclk_div", "hclk", 0, - clk_base + CLK_SYSTEM_RATE, 0, 2, 0, NULL); + clk_base + CLK_SYSTEM_RATE, 0, 2, 0, + &sysrate_lock); clk = clk_register_gate(NULL, "pclk", "pclk_div", CLK_SET_RATE_PARENT, clk_base + CLK_SYSTEM_RATE, 3, - CLK_GATE_SET_TO_DISABLE, NULL); + CLK_GATE_SET_TO_DISABLE, &sysrate_lock); clk_register_clkdev(clk, "pclk", NULL); clks[pclk] = clk; |