diff options
| author | Rhyland Klein <rklein@nvidia.com> | 2015-06-18 23:28:23 +0200 |
|---|---|---|
| committer | Thierry Reding <treding@nvidia.com> | 2015-11-20 18:05:02 +0100 |
| commit | 3706b43629f5b9fd4efce192da40ffa9412e75ee (patch) | |
| tree | 51dd671dcc551fbfdedf544179413acd019dcf63 /drivers/clk/tegra/clk-tegra20.c | |
| parent | clk: tegra: pll: Change misc_reg count from 3 to 6 (diff) | |
| download | linux-3706b43629f5b9fd4efce192da40ffa9412e75ee.tar.xz linux-3706b43629f5b9fd4efce192da40ffa9412e75ee.zip | |
clk: tegra: pll: Don't unconditionally set LOCK flags
SoC specific drivers should define the appropriate flags for each
PLL rather than relying on the registration functions to automatically
set flags on their behalf. This will properly allow for changes between
SoC generations where flags might be different and allow sharing the
same logic functions.
Reviewed-by: Benson Leung <bleung@chromium.org>
Signed-off-by: Rhyland Klein <rklein@nvidia.com>
Signed-off-by: Thierry Reding <treding@nvidia.com>
Diffstat (limited to 'drivers/clk/tegra/clk-tegra20.c')
| -rw-r--r-- | drivers/clk/tegra/clk-tegra20.c | 18 |
1 files changed, 10 insertions, 8 deletions
diff --git a/drivers/clk/tegra/clk-tegra20.c b/drivers/clk/tegra/clk-tegra20.c index d7da6fd8ca30..b49d94bc0b8f 100644 --- a/drivers/clk/tegra/clk-tegra20.c +++ b/drivers/clk/tegra/clk-tegra20.c @@ -291,7 +291,7 @@ static struct tegra_clk_pll_params pll_c_params = { .lock_enable_bit_idx = PLL_MISC_LOCK_ENABLE, .lock_delay = 300, .freq_table = pll_c_freq_table, - .flags = TEGRA_PLL_HAS_CPCON, + .flags = TEGRA_PLL_HAS_CPCON | TEGRA_PLL_HAS_LOCK_ENABLE, }; static struct tegra_clk_pll_params pll_m_params = { @@ -307,7 +307,7 @@ static struct tegra_clk_pll_params pll_m_params = { .lock_enable_bit_idx = PLL_MISC_LOCK_ENABLE, .lock_delay = 300, .freq_table = pll_m_freq_table, - .flags = TEGRA_PLL_HAS_CPCON, + .flags = TEGRA_PLL_HAS_CPCON | TEGRA_PLL_HAS_LOCK_ENABLE, }; static struct tegra_clk_pll_params pll_p_params = { @@ -323,7 +323,8 @@ static struct tegra_clk_pll_params pll_p_params = { .lock_enable_bit_idx = PLL_MISC_LOCK_ENABLE, .lock_delay = 300, .freq_table = pll_p_freq_table, - .flags = TEGRA_PLL_FIXED | TEGRA_PLL_HAS_CPCON, + .flags = TEGRA_PLL_FIXED | TEGRA_PLL_HAS_CPCON | + TEGRA_PLL_HAS_LOCK_ENABLE, .fixed_rate = 216000000, }; @@ -340,7 +341,7 @@ static struct tegra_clk_pll_params pll_a_params = { .lock_enable_bit_idx = PLL_MISC_LOCK_ENABLE, .lock_delay = 300, .freq_table = pll_a_freq_table, - .flags = TEGRA_PLL_HAS_CPCON, + .flags = TEGRA_PLL_HAS_CPCON | TEGRA_PLL_HAS_LOCK_ENABLE, }; static struct tegra_clk_pll_params pll_d_params = { @@ -356,7 +357,7 @@ static struct tegra_clk_pll_params pll_d_params = { .lock_enable_bit_idx = PLLDU_MISC_LOCK_ENABLE, .lock_delay = 1000, .freq_table = pll_d_freq_table, - .flags = TEGRA_PLL_HAS_CPCON, + .flags = TEGRA_PLL_HAS_CPCON | TEGRA_PLL_HAS_LOCK_ENABLE, }; static const struct pdiv_map pllu_p[] = { @@ -379,7 +380,7 @@ static struct tegra_clk_pll_params pll_u_params = { .lock_delay = 1000, .pdiv_tohw = pllu_p, .freq_table = pll_u_freq_table, - .flags = TEGRA_PLLU | TEGRA_PLL_HAS_CPCON, + .flags = TEGRA_PLLU | TEGRA_PLL_HAS_CPCON | TEGRA_PLL_HAS_LOCK_ENABLE, }; static struct tegra_clk_pll_params pll_x_params = { @@ -395,7 +396,7 @@ static struct tegra_clk_pll_params pll_x_params = { .lock_enable_bit_idx = PLL_MISC_LOCK_ENABLE, .lock_delay = 300, .freq_table = pll_x_freq_table, - .flags = TEGRA_PLL_HAS_CPCON, + .flags = TEGRA_PLL_HAS_CPCON | TEGRA_PLL_HAS_LOCK_ENABLE, }; static struct tegra_clk_pll_params pll_e_params = { @@ -411,7 +412,8 @@ static struct tegra_clk_pll_params pll_e_params = { .lock_enable_bit_idx = PLLE_MISC_LOCK_ENABLE, .lock_delay = 0, .freq_table = pll_e_freq_table, - .flags = TEGRA_PLL_FIXED, + .flags = TEGRA_PLL_FIXED | TEGRA_PLL_LOCK_MISC | + TEGRA_PLL_HAS_LOCK_ENABLE, .fixed_rate = 100000000, }; |