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| author | Thierry Reding <treding@nvidia.com> | 2015-04-20 15:10:43 +0200 |
|---|---|---|
| committer | Thierry Reding <treding@nvidia.com> | 2016-04-28 12:41:49 +0200 |
| commit | eede7113aabd3f40f8d9c32b1690f2859fcb101a (patch) | |
| tree | ffa6885caeb0e7e1a1e1a64161a4082771cceedc /drivers/clk/tegra/clk-tegra210.c | |
| parent | clk: tegra: Add dpaux1 clock (diff) | |
| download | linux-eede7113aabd3f40f8d9c32b1690f2859fcb101a.tar.xz linux-eede7113aabd3f40f8d9c32b1690f2859fcb101a.zip | |
clk: tegra: dpaux and dpaux1 are fixed factor clocks
The dpaux (on Tegra124 and Tegra210) and dpaux1 (on Tegra210) are fixed
factor clocks (1:17) and derived from pll_p_out0 (pll_p). They also have
a gate bit in the peripheral clock registers.
Signed-off-by: Thierry Reding <treding@nvidia.com>
Diffstat (limited to '')
| -rw-r--r-- | drivers/clk/tegra/clk-tegra210.c | 8 |
1 files changed, 8 insertions, 0 deletions
diff --git a/drivers/clk/tegra/clk-tegra210.c b/drivers/clk/tegra/clk-tegra210.c index 4f72d1a4347b..8133f92361fc 100644 --- a/drivers/clk/tegra/clk-tegra210.c +++ b/drivers/clk/tegra/clk-tegra210.c @@ -2462,6 +2462,14 @@ static __init void tegra210_periph_clk_init(void __iomem *clk_base, 1, 2); clks[TEGRA210_CLK_XUSB_SS_DIV2] = clk; + clk = tegra_clk_register_periph_fixed("dpaux", "pll_p", 0, clk_base, + 1, 17, 181); + clks[TEGRA210_CLK_DPAUX] = clk; + + clk = tegra_clk_register_periph_fixed("dpaux1", "pll_p", 0, clk_base, + 1, 17, 207); + clks[TEGRA210_CLK_DPAUX1] = clk; + /* pll_d_dsi_out */ clk = clk_register_gate(NULL, "pll_d_dsi_out", "pll_d_out0", 0, clk_base + PLLD_MISC0, 21, 0, &pll_d_lock); |